Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.     

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.This work was partially supported by NSF grant MIP-9409905, a 1993–94 ACM/IEEE Design Automation Scholarship and a grant from Nissan Corporation. A preliminary version of this work appeared in A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators, in Proc. of IEEE International Conference on Computer Design, Oct. 1994, pp. 292–295, where it received the ICCD'94 Best Paper Award.     

可编程数据平面技术综述

在软件定义网络中,可编程数据平面提供的编程能力是网络功能虚拟化的基石。可编程数据平面技术的核心是可编程能力与数据包处理性能。首先从数据平面的可编程性出发,探讨现有数据平面的数据包处理抽象。然后,分别对数据平面实施的目标平台与对应平台上的主要流表算法进行介绍,详细论述现有数据平面技术。最后,探讨了高性能数据平面技术存在的关键挑战。     

一种综合射频系统SCA软件平台的设计与实现

针对机载综合射频开放式系统架构,为了在软件综合层面上实现波形应用软件与具体平台的解耦,设计并实现了一种基于软件通信架构(Software Communication Architecture, SCA)的软件平台及其环境工具,解决了机载平台软件的分布式通信、资源调度管理、系统建模等技术问题,从而实现功能、应用和波形的组件化与动态重构。测试验证与工程应用情况表明,软件平台能够满足机载领域信号、信息处理强实时、高可用的应用需求,可有效提升综合射频系统软件开发质量与集成联试效率。     

基于误码率的软件无线电射频干扰效应分析

针对通信系统工作过程中受到外界电磁干扰而无法通信的问题,研究了基于软件无线电的电磁干扰效应及误码特征。通过分析典型软件无线电电磁信号传输特性及其信息链路电磁干扰耦合路径,设计了软件无线电通信干扰实验系统。该系统利用Simulink软件观测、记录通信信号眼图、星座图信息等受扰特征,并通过分析接收信号的误码率,给出了不同干扰信号对通信系统的影响规律：当同频干扰功率达到-40 dBm时通信开始出现误码,干扰功率每增加5 dB,误码率增加一个量级,干扰功率增加到-18 dBm时,误码率达到阈值0.25;邻频干扰误码率随干扰功率变化趋势与同频干扰一致,但出现误码的最小干扰功率更大;带外强干扰信号也会影响通信系统可靠性,在相同误码率情况下,需要更大的干扰信号功率且大小与信号频偏成正比。     

航空机载软件全数字仿真测试系统的设计与实现

针对航空机载软件测试环境与开发环境冲突、测试环境可控性和通用性差、非干预性测试困难的问题,分析了全物理实装测试环境、半实物仿真测试环境的优缺点,研究了全数字仿真测试技术,设计并实现了一种航空机载软件全数字仿真测试系统。该系统由仿真核心平台、仿真工具组件、协同仿真组件和人机交互组件构成,提供了航空机载处理器、内存、外设等多种可重用库。提出了基于底层虚拟机的动态二进制翻译技术、协同仿真时间同步和数据通信机制等关键技术,实现了航空机载软件全数字高速闭环仿真运行。工程实践证明,该系统能达到降低硬件设备的依耐性、简化测试环境搭建的复杂度、提高测试效率约42%的目的。     

一种波形可移植性量化评估的模糊综合评判法

要实现高效低成本的波形跨平台移植,需要通过量化评估优选出可移植性强的波形来进行移植。针对波形可移植性量化评估重要性,分析了影响波形可移植性量化评估的重要因素,提出了一种有效的波形可移植性量化评估模糊综合评判法,以软件无线电硬件平台因素为例论述了该方法的实现原理及流程。通过验证表明,该方法合理可行,具有很好的应用价值。     

采用射频直采技术的超宽带软件无线电平台

针对现代无线电系统对超宽带、可重构、多功能等需求日益增长的问题,基于射频直接采样技术,构建了一套符合PXI(PCI extensions for Instrumentation)标准的通用化超宽带软件无线电平台,硬件上以数模转换芯片AD9173和模数转换芯片ADC083000为核心,直接采样率高达3 Gsample/s;采用20 nm工艺制程的UltraScale Kintex FPGA,以IP(Intellectual Property)化开发理念设计FPGA固件,实现用户可编程。该平台能够满足0.1~1.4 GHz超宽带软件无线电应用需求,瞬时带宽高达1.3 GHz。