基于TMS320VC5410的最小系统设计

TMS320VC5410是TI公司生产的一款定点数字信号处理(DSP)芯片。基于DSP的最小系统是以其简洁的硬件结构来实现DSP的一般功能,广泛应用于工业生产、教学、科研、电子设计等领域。主要介绍了基于TMS320VC5410的最小系统硬件电路设计方案,阐述了重要电路部分的抗干扰设计和软件调试过程中应注意的若干问题。最后提出了简单易行的软件调试方法以及部分程序代码。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors

This paper proposes a software pipelining framework, CALiBeR (ClusterAware Load Balancing Retiming Algorithm), suitable for compilers targetingclustered embedded VLIW processors. CALiBeR can be used by embedded systemdesigners to explore different code optimization alternatives, that is, high-qualitycustomized retiming solutions for desired throughput and program memory sizerequirements, while minimizing register pressure. An extensive set of experimentalresults is presented, demonstrating that our algorithm compares favorablywith one of the best state-of-the-art algorithms, achieving up to 50% improvementin performance and up to 47% improvement in register requirements. In orderto empirically assess the effectiveness of clustering for high ILP applications,additional experiments are presented contrasting the performance achievedby software pipelined kernels executing on clustered and on centralized machines.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.     

可靠性试验样本量和截尾时间的计算

可靠性寿命试验中，一般都因受到费用和时间的限制，因此要用截尾试验获得信息，再据此对其可靠性进行统计推断，用非参数估计的方法探讨了进行可靠性试验的样本量或截尾时间的估计方法。     

氪灯和氙灯光谱强度分布和光谱效率测量

氪灯、氙灯光谱强度分布和光谱效率测量是反映氪灯、氙灯性能的关键指标。介绍了一套新型的氪灯、氙灯光谱强度分布和光谱效率检测系统。该系统是一套测量连续发光灯和脉冲闪光灯发光性能及效果的综合检测设备。该检测单元采用计算机进行操控,人机界面良好,便于检验人员进行氪灯和氙灯光谱强度分布和光谱效率的批量检测。检验人员利用该系统可进行装机模拟试验和可靠性试验,可对氪灯和氙灯的性能进行必要的分析研究,不断地积累了氪灯和氙灯的检验数据和经验。     

Calibrating software reliability models when the test environment does not match the user environment

Software failures have become the major factor that brings the system down or causes a degradation in the quality of service. For many applications, estimating the software failure rate from a user's perspective helps the development team evaluate the reliability of the software and determine the release time properly. Traditionally, software reliability growth models are applied to system test data with the hope of estimating the software failure rate in the field. Given the aggressive nature by which the software is exercised during system test, as well as unavoidable differences between the test environment and the field environment, the resulting estimate of the failure rate will not typically reflect the user‐perceived failure rate in the field. The goal of this work is to quantify the mismatch between the system test environment and the field environment. A calibration factor is proposed to map the failure rate estimated from the system test data to the failure rate that will be observed in the field. Non‐homogeneous Poisson process models are utilized to estimate the software failure rate in both the system test phase and the field. For projects that have only system test data, use of the calibration factor provides an estimate of the field failure rate that would otherwise be unavailable. For projects that have both system test data and previous field data, the calibration factor can be explicitly evaluated and used to estimate the field failure rate of future releases as their system test data becomes available. Copyright © 2002 John Wiley & Sons, Ltd.     

A simple electronic speckle shearing interferometer

A new speckle shearing interferometer with simple setup is proposed. The interferometer can be converted easily from a speckle referenced speckle pattern interferometer into a speckle shearing interferometer and vice versa. A beamsplitter and a mirror are used to generate the shear. The amount of shear can be adjusted by simply rotating the mirror. The costs involved are low and it is particularly useful for fast inspection in non-destructive testing of structural integrity. Both the theoretical studies of the method of measurement and the experimental results are presented.     

Statistical Inference with Fractional Brownian Motion

We give a test between two complex hypothesis; namely we test whether a fractional Brownian motion (fBm) has a linear trend against a certain non-linear trend. We study some related questions, like goodness-of-fit test and volatility estimation in these models.     

基于自适应预测滤波理论的模数转换器设计方法

基于自适应差分量化理论，提出了在不增加转换位数的情况下提高模数转换器(ADC)动态范围的一种设计方法。该方法通过量化输入与预测的差值来获得预测增益，从而扩大ADC的动态范围；通过差分量化值与预测值相加得到输出信号，并将该分别采用LMS和RLS算法进行处理．得到输入信号的预测值．计算机模拟结果证实，上述两种算法均能使模数转换器的动态范围提高约25dB．比较而言，RLS算法收敛速度更快，收敛性更好，但计算量较大．