基于DELPHI的镍氢电池管理系统软件设计

通过对镍氢电池性能的研究，给出了一个应用ISA总线技术构建的、基于DELPHI编程平台的镍氢电池管理系统的设计方案，重点介绍了该系统的软件技术和实现方法。     

对求解非线性方程方法的探索

BaiCL在2001年提出了双曲函数法，并把解设成具体的双曲函数，即sinhw和coshw的线性组合．本文把解设成是由2个函数f(ξ)和g(ξ)组成的线性组合，它们可以有多种取法，从而使方程更直接、更有效．借助数学软件Maple，用改进后的方法和吴文俊消元法，求解Bai C L文中的一个例子，获得了包含Bai文结果在内的更为丰富、精确的行波解．     

Standardization of BSE rapid test performances and experiences gathered during the implementation of large-scale testing

The accumulation of pathological prion protein is used as a diagnostic marker for transmissible spongiform encephalopathies. According to European Union (EU) regulations cattle older than 30 months of age (Germany, France, Italy, and Spain by national law >24 months) and slaughtered for human consumption must be tested by using rapid tests for bovine spongiform encephalopathy (BSE). Likewise fallen stock and clinically affected animals must be tested. This article gives a short overview of the incidence of BSE in Europe. The diagnostic hierarchy, i.e., the officially approved methodology for the confirmation of suspect rapid test cases, and the organization of the numerous laboratories involved in this large-scale testing for BSE are described. Special emphasis is given to necessary quality control measures currently in place for BSE rapid testing laboratories and to measures intended to assure a consistent performance of the commercially available rapid test kits.Presented at BERM-9—Ninth International Symposium on Biological and Environmental Reference Materials, 15–19 June 2003, Berlin, Germany.     

Quality assurance for the analytical data of micro elements in food

The micro element content of food is an important quality index due to the action of these elements on human health. In this article, we discuss how to ensure the reliability of analytical data on micro elements in order to truly represent the condition of food. Sampling, treatment of the analytical sample, selection of the analytical method, standard solution, and certified reference material, blank test, calibration of the instrument and equipment, application of the quality control chart, assessment of the final analytical result, and quality assurance system are briefly described. Received: 5 July 2001 Accepted: 19 November 2001     

W‐band physical layer design issues in the context of the DAVID–DCE experiment

This paper aims at focusing on the aspects concerning the physical layer design for an innovative satellite communication experiment. Such an experiment, denoted by the acronym DAVID–DCE (Data and Video Interactive Distribution—Data Collection Experiment) is based on the exploitation of the W‐band (75–110 GHz) for high‐bit‐rate satellite transmission. The potential advantages of using of the W‐band are mainly related to the great bandwidth availability, and to the absence of interference. Moreover, an expected result of the experiment is a substantive improvement in the communication system's performances in the presence of meteorological phenomena (e.g. rain) as compared with the more conventional Ka‐band satellite transmission. On the other hand, problems to be faced concern the non‐ideal behaviours of hardware devices employed for high‐frequency digital transmission. In particular, carrier recovery and timing recovery are the most crucial signal‐processing tasks to be carefully considered in the design of the physical level of the system, because they considerably suffer from hardware impairments. The purpose of this work is to illustrate the proposed solutions in terms of the most critical modulation, demodulation and synchronization design issues, together with the effects of non‐ideal behaviours of hardware components on BER performances. Copyright © 2004 John Wiley & Sons, Ltd.     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

软件:有效数字化广告牌背后的"大脑"

日益精密且成本逐渐下降的的显示技术使人们对下一代户内、户外广告的"数字化"充满了期待。然而运行显示网络必不可少的"大脑"是不容忽略的。下面综述了成功的数字广告系统的软件需求,以及这些系统的工作方式。