用DSP实现多目标实时跟踪

介绍了在 TMS3 2 0 C62 0 3上实现 4个目标的快速跟踪技术。为了提高实时性和精确度 ,采用线性汇编优化实现。1个 3 2 0× 160主窗口的 DSP平均处理时间为 2 m s,3个 60× 60副窗口的 DSP平均处理时间各为 0 .4ms,实现了复杂背景下低对比度目标的快速跟踪。实验结果证明跟踪效果良好 ,解决了以前窗口开不大、跟踪速度慢的问题     

逻辑分析仪在教学实验中的应用

硬件教学实验必须由验证性向设计性转变，才能达到培养学生设计能力和处理问题的能力。而逻辑分析仪是数字系统设计的常用工具．对于实验和教学都起着不可忽视的作用。     

基于TS101的PCI接口高速数据采集系统的设计

给出了基于TS101和PCI的双通道数据采集处理系统的设计方案。首先介绍了ADI公司新型数字信号处理(DSP)微处理器TS101和FLYBY数据传输模式,阐述了系统结构和工作原理,最后对如何利用TS101的FLYBY接口提高数据采集、存取效率和数据系统的逻辑控制进行了详细的论述。     

一种基于空间到达角的卫星电子侦察信号分选方法

在建立简化的卫星电子侦察空间模型的基础上，提出了一种利用空间到达角分选卫星电子侦察信号的新方法。通过仿真实验验证了这种方法的可行性。该方法可用于密集信号的预处理。     

无线电车载监测站的信号采集与通讯系统

本系统采用LabVIEW对无线电监测信号进行采集和处理．并开发用户界面。在Delphi平台上运用远程访问服务实现了无线电车载监测站与中心固定站的通讯。LabVIEW主程序对通讯子程序进行调用。     

基于VXI总线的超宽带线性调频信号源的设计

主要介绍了VXI总线C尺寸超宽带线性调频信号源的设计方法，重点描述了利用现场可编程逻辑器件FPAG和DSP设计VXI总线接口电路，以及数字波形存储直读技术在线性调频信号源中的应用。     

基于CAN总线的舵机控制系统设计

主要介绍了一种基于CAN总线的舵机控制系统。系统以CAN总线作为通信方式，PWM控制信号通过硬件方式产生，具有结构简单、信号稳定和实时性强的特点。     

Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).