FPGA动态可重构技术原理及实现方法分析

FPGA动态重构技术主要是指对于特定结构的FPGA芯片,在一定的控制逻辑的驱动下,对芯片的全部或部分逻辑资源实现在系统的高速的功能变换,从而实现硬件的时分复用,节省逻辑资源。本文以SRAM FPGA的可重配置特性为基础,结合几种新型的动态重构FPGA芯片结构,分析了FPGA动态重构技术的原理,讨论了其实现方法。     

一种低开销的旁路重构RO的片上老化测量方案

芯片老化引发的可靠性问题日益严重,会降低芯片性能,最终可能导致芯片失效。针对已有的芯片老化测量结构硬件开销大、影响关键路径时序等问题,提出了一种低开销的旁路重构振荡环的片上老化测量方案。实验结果表明,相比现有方案,该方案硬件开销降低了63.2%,在性能上平均提高了15.7%,并且老化在线测量误差较小,仅为2%。     

配电网综合自动化系统在高速公路隧道中的应用

雪峰山隧道工程采用了专用光纤、以太网作为通信系统,专用的后台配电网自动化系统具有较为完善的构架。配电网络采用了双环网供电,在双环之间采用两路联络开关,其结构相对复杂。针对配网自动化系统故障诊断、隔离与网架重构进行了详细的论述,其中对外部电源故障实现配电自动化方案做了重点论述,此配网自动化实现方案可靠有效的实现了工程的配电网自动化,保证了整个供电系统的可靠运行。     

Shape Reconfiguration of a Biomimetic Elastic Membrane with a Switchable Janus Structure

A method for the fabrication of a biomimetic Janus composite membrane is reported here. This approach is based on a membrane with a vertical gradient crosslinking degree, which is achieved through UV light–induced dimerization of anthracene grafted on poly(styrene‐block‐butadiene‐block‐styrene) chains in the presence of carbon nanotubes. UV light penetration is controlled by the accretion of carbon nanotubes to ultimately tailor the heterogeneous crosslinking degree in thickness. This kind of Janus structure is applied here for shape actuation. Here, solvent or shape memory effect–induced shape morphing is obtained via the heterogeneous swelling (deswelling) abilities of, or internal stress from, the Janus structure. By tailoring the UV light irradiation time, the irradiated region and the prestrain, sophisticated and multiple types of shape morphing are programed. In addition, this type of Janus structure can shift back to the homogeneous structure via dedimerization of the anthracene dimers upon thermal treatment, which provides extensive freedom for the design of smart responsive actuators.     

Reconfigurable and Renewable Nano-Micro-Structured Plastics for Radiative Cooling

Passive radiative technology enables sustainable cooling by synchronously emitting heat and reflecting solar light without any energy consumption. However, the consumption of non-recyclable and non-renewable radiative materials in large quantities may eventually cause resource waste and environmental issues. Herein, reconfigurable and renewable nano-micro-structured plastics for future eco-friendly and large-scale radiative cooling applications are developed. The plastics are facilely prepared from a locally confined polymerization method, which not only enables the customization of nano/micro-structures for thermal emission and sunlight reflection but also provides physically cross-linked networks for damage repairing, shape reconfiguration, and recyclable usage. Compared with traditional plastics applied on electronic devices, the nano-micro-structured plastic achieves much higher cooling efficiency with a temperature drop of 8.6 °C on electronic circuits and 7.5 °C cooling improvements under sunlight. With the excellent cooling performance and the recycling potential, the nano-micro-structured plastics open an environmentally sustainable pathway to address the thermal issues encountered by electronic devices and challenges of global warming.     

基于数据缓存重配置的多核间数据交换方法

为了实现多核处理器的各CPU核执行的程序之间数据共享与同步,本文提出了一种基于数据缓存重配置的多核间数据交换方法。该方法充分利用内部数据缓存,采用数据缓存重配置的方式,对每个处理内核具有的独立的数据缓存进行容量和地址空间的重新配置,通过对部分数据缓存的互相转让来实现数据的交换,实现了核间数据的快速、可靠交换,且容易实现。     

一种应用WR和OBS混合结构

密集波分复用（DWDM）技术的发展为光网络带来了新的应用前景,它是高带宽需求最好的解决方法之一.本文给出了光突发交换和波长路由两种技术的基本特征,并讨论了每个实现机制的优缺点,提出了融合这两种技术以克服使用单一方式的限制的新结构.     

Characterization, testing and reconfiguration of faults in mesh networks

Achieving fault-tolerance through incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and its reconfiguration capabilities. Such fault patterns are called catastrophic fault patterns (CFPs). In this paper, we characterize catastrophic fault patterns in mesh networks when the links are bidirectional or unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a fault pattern is catastrophic. When a fault pattern is not catastrophic we study the problem of finding optimal reconfiguration strategies, where optimality is with respect to either the number of processing elements in the reconfigured network (the reconfiguration is optimal if such a number is maximized) or the number of bypass links to activate in order to reconfigure the array (the reconfiguration is optimal if such a number is minimized). The problem of finding a reconfiguration strategy that is optimal with respect to the size of the reconfigured network is NP-complete, when the links are bidirectional, while it can be solved in polynomial time, when the links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we provide algorithms which efficiently find an optimal reconfiguration.     

Multi-modes control method for spacecraft formation establishment and reconfiguration near the libration points

This paper studies Multi-modes control method for libration points formation establishment and reconfiguration. Firstly, relations between optimal impulse control and Floquet modes are investigated. Method of generating modes is proposed. Characteristics of the mode coefficients stimulated at different time are also given. Studies show that coefficients of controlled modes can be classified into four types, and formation establishment and reconfiguration can be achieved by multi-impulse control with the presented method of generating modes. Then, since libration points formation is generally unstable, mutli-modes keeping control method which can stabilize five Floquet modes simultaneously is proposed. Finally, simulation on formation establishment and reconfiguration are carried out by using method of generating modes and mutli-modes keeping control method. Results show that the proposed control method is effective and practical.     

Run-time management of systems with partially reconfigurable FPGAs

Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems by swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a Run-Time System Manager (RTSM) for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions (RRs) of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM controls system operation considering the status of each task and region (e.g. busy, idle, scheduled for reconfiguration/execution, etc). Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and region reservation for future reconfiguration and execution. We validate the correctness and portability of our RTSM executing an image processing application on two Xilinx-based platforms: ZedBoard and XUPV5. We also perform a more extensive evaluation of its features using a simulation framework, and find that – despite the technology limitations – our approach can give promising results in terms of scheduling quality. Since our RTSM supports also the scheduling of parallel SW tasks, we use it to manage the execution of the entire parallel Edge Detection application on a desktop; we compare the application execution time with that using the OpenMP framework and find that with our RTSM execution is 2.4 times faster than the unoptimized OpenMP version. When processor affinity optimization is enabled for OpenMP, our RTMS and the OpenMP are on par, indicating that the scheduling efficiency of our RTSM is competitive to this state-of-the-art scheduler, while supporting in addition the management of HW tasks.