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1.
多版本软件通过设计相异性实现了软件容错。为了对这种方法进行研究,我们的课题实现了一个三版本软件系统,称之为SFTMP(SoftwareFault-TolerantMultiProcessor)。本文描述了SFTMP的硬件结构和软件执行支持环境,该环境包括同步、表决和监控功能、版本间的通讯及故障的恢复和重构。 相似文献
2.
《Mechatronics》2016
Today, in domains like automation and robotics systems consist of various sensors and computation nodes. Due to the temporal dependency in quality of measured data, such Cyber-Physical Systems (CPS) commonly have real-time requirements on communication. In addition, these systems shall become more flexible and scalable, e.g., by adding new components to the CPS. This would be most suitable if a CPS could react to the presence of a new component and reconfigure itself to run afterward with the new component integrated to the CPS. This capability is covered by the term Plug-and-Produce. In this paper, we propose a concept to enable Plug-and-Produce within a CPS whose network uses different communication media, e.g., Ethernet and CAN. To enable real-time communication provided by different communication protocols, their different synchronization mechanisms have to be combined to get a common time base within the entire system. For this purpose, we consider Ethernet as well as CAN-based real-time communication protocols and their synchronization mechanisms. The proposed concept for self-reconfiguration aims to be integrated into our three layered software architecture that is presented as well. 相似文献
3.
4.
The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor /intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs. 相似文献
5.
针对一般调制平台互联性差、灵活性差、复用性差等问题,采用软硬件协同设计和部分动态可重配置等技术,设计了一种基于Zynq-7000和AD9361的通用调制平台。采用16APSK和QPSK的调制方式对通用调制平台的设计进行验证,其中平方根升余弦成形滤波器采用查找表形式的多相滤波器结构实现,该实现方法只用到加法运算。测试结果表明,在不同Zynq-7000开发板和不同调制方式下,替换部分硬件功能模块和修改软件配置,平台均能正常工作。与传统调制平台相比,本平台的设计以及功能实现具有灵活性强、复用性高等特点,具有广阔应用前景。 相似文献
6.
解决虚拟网动态加入、离开导致的底层网络资源占用不均衡问题,提出基于预测的资源重配置算法(FRRA)。FRRA用已知信息预测资源重配置时间间隔,代替已有算法中周期性时间间隔。采取两方面措施保证重配置时机全局最优:将资源划分为关键资源和普通资源并使用不同配置算法;根据资源迁移失败概率,推导重配置请求次数极限值。与算法VNA-II、PMPA实验比较表明,FRRA的重配置花费比VNA-II节省69%,比PMPA节省42%;FRRA的虚拟网请求接收率比VNA-II提高29%,比PMPA提高52%。 相似文献
7.
Elena Moscu Panainte Koen Bertels Stamatis Vassiliadis 《The Journal of VLSI Signal Processing》2006,43(2-3):161-172
In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology.
As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application.
Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the
compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number
of executed hardware configuration instructions taking into account constraints such as the “FPGA-area placement conflicts”
between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions
up to the application’s main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order
of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up
to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution. 相似文献
8.
配电网重构一般采用对单一目标优化,而配电网重构却是一个多目标优化问题。因此,在此提出了基于小生境思想的遗传算法,以配电网的经济性、安全性和供电可靠性为目标,并采用Pareto寻优方式,得出Pareto最优解集,实现了和以往不同的另一种寻优方式,即先寻优后决策。在寻优过程中,通过小生境环境和交叉率和变异率的自适应机制,提高了遗传算法的全局收敛能力和收敛速度,并通过算例验证了方法的有效性。 相似文献
9.
A switchable Yagi-Uda antenna prototype with radiation pattern reconfiguration is presented in this letter. The proposed reconfigurable antenna is based on the concept of switching between the reflector and director of a Yagi-Uda antenna using a radio frequency PIN diode. As a result, the minimum/maximum radiation can be steered towards desired signals or away from interfering signals in opposite directions. The measured 10 dB impedance bandwidth and gain are 210 MHz (7%) and 8.02 dBi at 3 GHz, respectively. Details of the antenna design and its performance are described and empirically analyzed. 相似文献
10.
结合SINS/GPS/DVL组合导航系统各子系统的特点,提出了一种新的容错设计方案。此方案采用并列运行的滤波器族结构,该结构可以提供不受污染的最优解,且具有容错性好和系统输出数据热备份等优点。仿真结果表明,此方案既可有效地监测和隔离系统故障,同时保证了系统的精度。 相似文献