脉冲高功率离子二极管的动力学模拟

基于等离子体的爆炸发射模型,利用自洽的2.5维的胞中粒子（PIC）模拟程序MAGIC模拟了平板型磁绝缘离子二极管中电子和质子的动力学特性。给出了电压为300kV,外加磁场为2倍临界磁场情况下的二极管特性,阴阳极间隙中带电粒子的空间和相空间分布,以及净电荷密度分布和电场分布,结果表明,引出束流密度比单离子Child-Langmuir公式计算的结果大5倍;外加磁场导致在阴极附近形成虚阴极。空间电荷使得阴阳极间隙中电场扰动和增强。     

光阴极注入器型能量回收射频加速器

光阴极注入器型能量回收射频加速器（PERL）是新一代加速器,在高平均功率自由电子激光和下一代高亮度光源等研究中有很好的应用前景。分析了PERL的强流与高平均功率特性,对注入器输出束流品质的要求及光阴极注入器、超导加速腔等关键技术进行了研究,设计分析了一种特殊结构的高压DC Gun光阴极注入器,能有效地提高DC加速腔中的加速场强,当高压为1MV和加速场达到10MV/m时,产生的电子束流能够基本满足PERL应用要求。同一超导加速段中的束流加速和能量回收的数值模拟计算结果表明,能获得高效率电子束流能量回收效果。     

预脉冲对相对论磁控管工作性能的影响分析

在阐述预脉冲产生的基础上,分析了预脉冲带来的一系列影响,包括工和电压波形变化,提前生成等离子体,以及预脉冲阶段放大竞争模式等,这些影响与相对论磁控管起振工作频率相联系,从而直接造成了相对论磁控管的基本性能参数,如脉宽、工作频率及输出功率等变化。结合具体实验,对比了有、无预脉冲条件下相对论磁控管工作性能的差异,对预脉冲的影响因素与相对论磁控管性能之间的联系进行了详细的分析。     

监管技术巨头：技术力量作为市场支配地位认定因素之再审视

如何有效规制技术巨头已然成为当前《反垄断法》修订的重要任务。技术力量虽然作为传统的市场支配地位认定要素,但长期以来呈现被虚置化的客观状态,致使技术巨头市场支配地位的认定难度增大,技术力量自身的传导效应被显著低估。数字技术对市场竞争的影响异于以往,其通过平台、数据、算法的数字市场三维结构框架影响生产与交易的全过程。技术与三维结构结合所形成的技术力量极为强大,超越了以控制价格为主的传统市场力量,结合社会与资本力量形成了更牢固的市场固化结构。在判断技术巨头的市场支配地位时,亟需发挥技术力量作为非价格型认定要素的重要作用。应当摒弃虚置技术力量作为市场支配地位认定要素的固有症结,提高技术力量在认定市场支配地位时所占权重,回归结构性视角,妥善防范技术巨头无序扩张。     

手机企业的标准化战略研究

介绍了标准化战略的重要意义,对国内手机企业标准化现状做了分析和剖析,并为企业提供了标准化战略工作的方法对策.     

Adaptive Online Voltage Scaling Scheme Based on the Nash Bargaining Solution

In an effort to reduce energy consumption, research into adaptive power management in real‐time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.     

企业要有“三品”在手——PCB企业的软实力(7)

文章概要地说明PCB企业掌握三品的重要性。企业掌握了三品就掌握了市场的现在和未来,使企业永远处于良性循环的发展之中。     

An improved progressive preconditioning method for steady non‐cavitating and sheet‐cavitating flows

An improved progressive preconditioning method for analyzing steady inviscid and laminar flows around fully wetted and sheet‐cavitating hydrofoils is presented. The preconditioning matrix is adapted automatically from the pressure and/or velocity flow‐field by a power‐law relation. The cavitating calculations are based on a single fluid approach. In this approach, the liquid/vapour mixture is treated as a homogeneous fluid whose density is controlled by a barotropic state law. This physical model is integrated with a numerical resolution derived from the cell‐centered Jameson's finite volume algorithm. The stabilization is achieved via the second‐and fourth‐order artificial dissipation scheme. Explicit four‐step Runge–Kutta time integration is applied to achieve the steady‐state condition. Results presented in the paper focus on the pressure distribution on hydrofoils wall, velocity profiles, lift and drag forces, length of sheet cavitation, and effect of the power‐law preconditioning method on convergence speed. The results show satisfactory agreement with numerical and experimental works of others. The scheme has a progressive effect on the convergence speed. The results indicate that using the power‐law preconditioner improves the convergence rate, significantly. Copyright © 2010 John Wiley & Sons, Ltd.     

基于片上变压器耦合的CMOS功率放大器设计

设计了一个2 GHz全集成的CMOS功率放大器(PA),该PA的匹配网络采用片上变压器实现,片上变压器用来实现单端信号和差分信号之间的转换和输入、输出端的阻抗匹配。采用ADS Momentum软件对片上变压器进行电磁仿真,在2 GHz频点,输入、级间和输出变压器的功率传输效率分别为74.2%,75.5%和78.4%。该PA基于TSMC 65 nm CMOS模型设计,采用Agilent ADS软件进行电路仿真,仿真结果表明:在2.5 V供电电压、2 GHz工作频率点,PA的输入、输出完全匹配到50Ω(S11=–22.4 d B、S22=–13.5 d B),功率增益为33.2 d B,最高输出功率达到23.4 d Bm,最高功率附加效率(PAE)达到35.3%,芯片面积仅为1.01 mm2。     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.