Estimation of power density in IMPATT using different materials

ABSTRACT

The RF output power dissipated per unit area is calculated using Runge-Kutta method for the high-moderate-moderate-high (n⁺-n-p-p⁺) doping profile of double drift region (DDR)-based impact avalanche transit time (IMPATT) diode by taking different substrate at Ka band. Those substrates are silicon, gallium arsenide, germanium, wurtzite gallium nitride, indium phosphide and 4H-silicon carbide. A comparative study regarding power dissipation ability by the IMPATT using different material is being presented thereby modelling the DDR IMPATT diode in a one-dimensional structure. The IMPATT based on 4H-SiC element has highest power density in the order of 10¹⁰ Wm^?2 and the Si-based counterpart has lowest power density of order 10⁶ Wm^?2 throughout the Ka band. So, 4H-SiC-based IMPATT should be preferable over others for the power density preference based application. This result will be helpful to estimate the power density of the IMPATT for any doping profile and to select the proper element for the optimum design of the IMPATT as far as power density is concerned in the Ka band. Also, we have focused on variation of power density with different junction temperatures and modelled the heat sink with analysis of thermal resistances.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

光纤布拉格光栅的无源温度补偿

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平面阵列波导光栅波导模式参量的分析

用周期波导的方法分析平面阵列波导光栅(AWG)的本征方程及波导模式参数,结果表明波导传播常数是带状分布的,与波导间隔有关。分析结果对器件的优化设计有一定的指导意义。     

用CPLD实现SRAM工艺FPGA的安全应用

提出了一种利用CPLD产生的伪随机码来加密SRAM工艺FPGA的方法,并详细介绍了具体的电路和VHDL代码。     

半导体传感器在生物分析科学中的应用(英文)

回顾了半导体生化传感器 (ISFET 和 LA PS)在医学监测、免疫检测、免疫分析、D N A 杂交以及细胞培养等方面应用的进展。为使半导体器件适用于生化检测,对其中所采用的检测手段和取得的研究结果进行了分析。展望了通过与微流体网络相结合,基于半导体传感器的实验室芯片化的可行性。     

基于MFSK的多载波水声通信系统及实验研究

本文在深入研究水声通信信道特性及多载波关键技术的基础上,设计并研制了基于M FSK的高速自适应多载波水声通信系统,并进行了湖上实验。理论分析、仿真及湖上试验结果表明:基于M FSK的多载波水声通信系统,多径抑制有效,对同步的精确度要求不高,性能稳健,更适合于恶劣水声通信环境下、中距离(10~30km)较高数据率多载波通信系统,易于工程实现,具有良好的应用前景。     

机电制造企业生产系统的仿真

针对我国机电企业的现状，研究并完成了机电制造企业的物流监控信息系统的典型设计，建立了质量跟踪体系软件结构，进行计算机仿真，并应用于现场。研究涉及计算机控制技术、信息处理技术、工业以太网通讯技术、现场总线通讯技术、最优化策略等多学科技术。该系统可以大幅度提高生产效率、降低生产成本、减少库存和资金占用，减少日益昂贵的生产和库存用地。     

基于两层均匀媒质的GPEN SAR地下目标成像方法及其性能分析

地表穿透合成孔径雷达(Ground PENetration SAR,GPEN SAR)为了探测掩埋在地下的目标,通常工作在多层媒质的环境中。传统成像模型是建立在同一均匀媒质的假设上,不再适合于GPEN SAR的实际情况。本文首先建立了两层分区均匀媒质中的成像模型,然后利用后向投影(BP)算法定量分析了成像几何参数、土壤参数等对成像的影响,进而提出了一种修正的后向投影(MBP)算法。MBP算法不仅能够校正两层分区均匀媒质对成像定位的影响,还能估计目标的掩埋深度,提供目标三维位置坐标。仿真结果验证了MBP算法在不同信噪比环境下,对多目标的三维定位精度能满足实际的需要。     

2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.