高速Viterbi处理器—流水式块处理并行结构

本文提出一种流水式块处理并行Ｖｉｔｅｒｂｉ处理器，可以得到ＬＭ倍增速（Ｍ为流水级数，Ｌ为块长度），为达到更高速的Ｖｉｔｅｒｂｉ处理器提供了新型的并行结构。它可用Ｓｙｓｔｏｌｉｅ阵列构成，因而适于ＶＬＳＩ实现。     

环路流水线数字系统的最大速率

如何计算流水线系统的最大速率，这是文献［１～３］的著名结论。本文在建立一般模型的基础上，分析说明了在环路流水线中由于相移关系要受到约束，速率上限事实上要比先前的悲观。本文就边沿触发器和门闩为站寄存器的不同情况，证明了环路流水时最小周期的确定，等价于对一线性规划问题的求解。通过运行程序ＰＩＰＥ－ＬＰ，本文给出了若干系统的求解。     

VLSI 低功耗设计分析

本文从介绍电路功耗的基本概念及相关因素入手，按照VLSI自顶向下的设计流程，从算法，结构、逻辑和物理四个层面，系统全面地分析了低功耗VLSI设计技术。     

基于FPGA的弱小目标增强方法

针对强光背景低对比度条件下弱小目标的特点,提出基于Sigmoid函数的图像增强方法.该方法能扩展图像中像素较多的灰度,压缩像素较少的噪声.针对传统的Cordic算法,提出了一种基于查找表-流水线乘积(LTPM)的算法实现指数运算,运用该算法,在FPGA中很好地实现了本文提出的增强算法.     

基于优化回溯模型的无重叠模调度算法

软件流水技术通过重组循环体来挖掘指令级并行性,模调度是一类广泛使用的软件流水调度算法.传统模调度算法通常会产生变量活跃域重叠和寄存器压力增大问题,无法适用于嵌入式处理器.本文面向嵌入式处理器特性,建立了一种优化回溯模型,并基于该回溯模型提出了一种面向嵌入式处理器的无重叠模调度算法(NOn-Over-lapped Iterative Modulo Scheduling,简称NOOI).NOOI算法使用循环相关反依赖消除变量活跃域重叠,并使用依赖约束和资源约束回溯模型消解节点冲突,从而提高了模调度的有效性.实验结果表明,NOOI模调度算法能够有效改进模调度成功率和循环启动间距,并提高程序性能.     

基于FPGA和符号LMS算法的自适应滤波器设计

为了减少实现基于FPGA和LMS算法的自适应滤波器过多消耗硬件资源的问题,提出了符号LMS算法,通过降低乘法运算的次数来提高自适应滤波器的运行速度,并使用流水线技术进行优化。软件仿真验证了符号LMS算法的可行性,硬件仿真证实了采用该算法和流水线技术的自适应滤波器的优越性。     

一种基于不均衡数据的网络入侵流量分类方法

在网络入侵流量检测中,普遍存在不同攻击类型的流量分布不均现象,导致少数攻击流量类识别率较低.为解决此类问题,基于不同特征空间的分类器流水线组合方法将多分类问题转化为不同特征空间上的两分类问题,有效地实现少数类重抽样和特征空间的优化,避免了少数类受多数类特征的干扰.实验表明,此方法可以有效地提高攻击流量中少数类的分类精度和召回率.     

Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks

Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dataflow graphs have been widely regarded as a powerful programming model for DSP applications. In this paper we propose a method to minimize buffer storage requirement in constructing rate-optimal compile-time (MBRO) schedules for multi-rate dataflow graphs. We demonstrate that the constraints to minimize buffer storage while executing at the optimal computation rate (i.e. the maximum possible computation rate without storage constraints) can be formulated as a unified linear programming problem in our framework. A novel feature of our method is that in constructing the rate-optimal schedule, it directly minimizes the memory requirement by choosing the schedule time of nodes appropriately. Lastly, a new circular-arc interval graph coloring algorithm has been proposed to further reduce the memory requirement by allowing buffer sharing among the arcs of the multi-rate dataflow graph.We have constructed an experimental testbed which implements our MBRO scheduling algorithm as well as (i) the widely used periodic admissible parallel schedules (also known as block schedules) proposed by Lee and Messerschmitt (IEEE Transactions on Computers, vol. 36, no. 1, 1987, pp. 24–35), (ii) the optimal scheduling buffer allocation (OSBA) algorithm of Ning and Gao (Conference Record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Charleston, SC, Jan. 10–13, 1993, pp. 29–42), and (iii) the multi-rate software pipelining (MRSP) algorithm (Govindarajan and Gao, in Proceedings of the 1993 International Conference on Application Specific Array Processors, Venice, Italy, Oct. 25–27, 1993, pp. 77–88). Schedules generated for a number of random dataflow graphs and for a set of DSP application programs using the different scheduling methods are compared. The experimental results have demonstrated a significant improvement (10–20%) in buffer requirements for the MBRO schedules compared to the schedules generated by the other three methods, without sacrificing the computation rate. The MBRO method also gives a 20% average improvement in computation rate compared to Lee's Block scheduling method.     

FIR滤波器的优化设计与硬件实现

介绍如何用FPGA器件设计和实现FIR数字滤波器，对几种实现方案进行了比较和优化，并就如何改善所设计滤波器的性能和指标进行了讨论。     

Laplacian图像边缘检测器的FPGA实现研究

介绍了Laplacian边缘检测算法模型,边缘检测工作流程,分布式运算原理,阐述了用FPGA实现的一个Lapla—cian图像边缘检测器的设计,包括系统总体设计,主要模块的设计思想和系统仿真结果。该检测器采用了流水式数据输入和高速分布式卷积运算等技术,具有良好的实时处理性能,若系统工作时钟为100MHz,则处理一幅1024-1024的图像的时间仅需0．01s左右。