DC-DC变换器突加负载时的动态性能研究

提出了一种能够有效改善DC-DC变换器动态性能的方案。该方案是在全桥电路基础上并联一单端正激变换电路，使变换器负载从10%轻载突加到100%满载时，其暂态过程小于1μs输出电压达到设计要求。文中对具体电路进行了详细分析，并通过仿真进行了验证。     

A new microtensile tester for the study of MEMS materials with the aid of atomic force microscopy

An apparatus has been designed and implemented to measure the elastic tensile properties (Young's modulus and tensile strength) of surface micromachined polysilicon specimens. The tensile specimens are “dog-bone” shaped ending in a large “paddle” for convenient electrostatic or, in the improved apparatus, ultraviolet (UV) light curable adhesive gripping deposited with electrostatically controlled manipulation. The typical test section of the specimens is 400 μm long with 2 μm×50 μm cross section. The new device supports a nanomechanics method developed in our laboratory to acquire surface topologies of deforming specimens by means of Atomic Force Microscopy (AFM) to determine (fields of) strains via Digital Image Correlation (DIC). With this tool, high strength or non-linearly behaving materials can be tested under different environmental conditions by measuring the strains directly on the surface of the film with nanometer resolution.     

Tests of ordered hypotheses in linkage in heredity

The asymptotic null distribution of the likelihood ratio test for two cases of ordered hypotheses in a particular genetic model is considered. A simple iterative process is proposed in order to get the restricted estimates. It is shown that both tests have asymptotically a chi-bar squared distribution and the same size. A simulation study is also conducted in order to compare the usual unrestricted test with the corresponding one of ordered hypotheses. Finally, the results are extended to some special cases.     

总延误问题顺时安排法的性能比

给定一组工件的加工时间与工期，要求确定这些工件在一台机器上的加．工排列，使相应的总延误达到最小，这就是总延误问题．该问题在近年已被证明是NP困难的．由Wilkermn和Irwin（1971），林勋（1983）等所研究的顺时安排法能得到相邻交换意义下的局部解．在本文中，我们进一步证明该算法能得到前移邻域意义下的局部解，并确定了该算法的性能比．     

分组网与ISDN互连的性能分析

本文研究分组交换数据网与ＩＳＤＮ互连的性能分析，文中考虑了分组肉与窄带ＩＳＤＮ和宽带ＩＳＤＮ互连时信关所应完成的功能，分别给出了两种情况下的信关排队模型；在信关存储容量分别为有限和无限的情况下，对两种模型进行了求解，给出了阻塞概率和平均延迟的表达式。对于与Ｂ－ＩＳＤＮ互连的情况，提出了用开关确定性过程来描述输出排队的分组到达流，并提出了一种小时隙方法分析ＳＤＰ／Ｄ／１排队。     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

Turbo码综合性能分析与Turbo编码调制

对 Ｔｕｒｂｏ码的 ＲＳＣ分量码、交织器、调制方式、信道以及迭代译码算法进行了综合研究与性能分析，并给出了一种基于逐比特ＭＡＰ算法的Ｔｕｒｂｏ编码与多元调制相结合的编码调制方式。仿真结果表明，该方案将Ｔｕｒｂｏ码的高编码增益与多元调制的高频谱利用率有效地结合在一起，是一种功率和频谱高效的编码调制方式，比传统的ＴＣＭ方式有更好的性能。     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.