THE PARALLEL BLOCK ADAPTIVE MULTIGRID METHOD FOR THE IMPLICIT SOLUTION OF THE EULER EQUATIONS

A method capable of solving very fast and robust complex non-linear systems of equations is presented. The block adaptive multigrid (BAM) method combines mesh adaptive techniques with multigrid and domain decomposition methods. The overall method is based on the FAS multigrid, but instead of using global grids, locally enriched subgrids are also employed in regions where excessive solution errors are encountered. The final mesh is a composite grid with uniform rectangular subgrids of various mesh densities. The regions where finer grid resolution is necessary are detected using an estimation of the solution error by comparing solutions between grid levels. Furthermore, an alternative domain decomposition strategy has been developed to take advantage of parallel computing machines. The proposed method has been applied to an implicit upwind Euler code (EuFlex) for the solution of complex transonic flows around aerofoils. The efficiency and robustness of the BAM method are demonstrated for two popular inviscid test cases. Up to 19-fold acceleration with respect to the single-grid solution has been achieved, but a further twofold speed-up is possible on four-processor parallel computers.     

Modelling the motion of a disk Rolling on a curve in R: The case where the motion is driven by using two overhead rotors

This work deals with the modelling of the motion of a disk rolling without slipping ona regular curve in R³. The disk's motion is driven by a pedalling torque and by using two overhead rotors.     

一种适用于低功耗超长指令字DSP处理器的硬件循环缓冲设计

提出了用于VLI WDSP处理器的硬件循环缓冲器的设计.该DSP处理器在结构上利用了在信号处理程序中循环经常出现这一特点,专门设计了硬件循环处理模块用来消除因循环跳转造成的流水线等待,以达到循环的零开销处理从而提高DSP的性能.设计过程中为了减小硬件开销,对循环的长度特点进行了分析,把循环分类两类并用不同的方法处理.结果表明循环跳转的处理是在独立模块中操作,没有造成流水线的等待提高了性能,该硬件循环的面积是3 .8 k逻辑门.     

Parallelization of MRCI based on hole-particle symmetry

The parallel implementation of multireference configuration interaction program based on the hole-particle symmetry is described. The platform to implement the parallelization is an Intel-Architectural cluster consisting of 12 nodes, each of which is equipped with two 2.4-G XEON processors, 3-GB memory, and 36-GB disk, and are connected by a Gigabit Ethernet Switch. The dependence of speedup on molecular symmetries and task granularities is discussed. Test calculations show that the scaling with the number of nodes is about 1.9 (for C1 and Cs), 1.65 (for C2v), and 1.55 (for D2h) when the number of nodes is doubled. The largest calculation performed on this cluster involves 5.6 x 10(8) CSFs.     

Splitting graphs when calculating Myerson value for pure overhead games

A communication situation consists of a coalitional game and a graph, the nodes of the graph corresponding to the players of the game. To calculate the Myerson value for such situations, we obtain results which extend those well known for trees and cycle-complete graphs. On the other hand, in order to reduce the associated calculus for communication situations with a pure overhead game, the possibility of splitting the graph in several subgraphs is analyzed. For each fixed decomposition of the graph, a subspace of games compatible with this decomposition is given.     

On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages

A design-for-testability implementation for analogue functional blocks of mixed-signal ASICs is presented. For the analogue blocks direct access via an analogue input pin for the automated test equipment is required. To this end existing OpAmp or OTA stages of the respective analogue blocks are converted into simple clocked comparators. The resulting two-mode comparators are used to observe specific internal nodes of the functional block under test. Depending on the comparator mode, the observed test response evaluation can either be static and/or quasi-dynamic. At least two reference voltages are required each with two different levels determined by a hysteresis. All necessary reference voltages are generated on-chip in the central biasing cell of the ASIC. Due to this Design-for-Testability implementation, an on-chip test evaluation can be performed without the need to bring an analogue signal on- or off-chip. From simulation and measurement results of a feasibility study performed on a general purpose test circuit realised in 0.35 m technology, the applicability was demonstrated. It showed that good fault coverages in the analogue functional blocks can be achieved. Estimations about the biasing programming indicated that this technique is in particular suitable for mixed-signal ASICs larger than 15 mm² with a typical total power consumption of more than 50 mW typical for high voltage applications.     

Defending against wormhole attacks in mobile ad hoc networks

In ad hoc networks, malicious nodes can deploy wormhole attacks to fabricate a false scenario on the proximity relationship among mobile nodes. A classification of the attacks according to the format of the wormholes is proposed. This forms a basis to identify the detection capability of various approaches. An analysis shows that earlier approaches focus on the prevention of wormholes among neighbors that trust each other. As a more generic approach, we present an end‐to‐end scheme that can detect wormholes on a multi‐hop route. Only the trust between the source and the destination is assumed. The mechanism uses geographic information to detect anomalies in neighbor relations and node movements. To reduce the computation and storage overhead, we present a scheme called cell‐based open tunnel avoidance (COTA) to manage the information. COTA requires a constant space for every node on the path and the computation overhead increases linearly to the number of detection packets. We prove that the savings do not deteriorate the detection capability. Various schemes to control communication overhead are studied. The simulation and experiments on real devices show that the proposed mechanism can be combined with existent routing protocols to defend against wormhole attacks. Copyright © 2006 John Wiley & Sons, Ltd.     

DCC开销交叉技术在光传输网络中的应用

提出了一种利用DCC开销交叉技术建立DCC的解决方案,介绍了该方案的技术原理和实现途径,最后对该技术进行了测试验证,试验结果表明该技术方案是正确可行的。     

A forwarding strategy of counteracting redundancy data in named data networking

In named data networking, a router forwards Interests to all available contents including copies under the original design of forwarding strategy. All of these redundant copies of requested contents are returned to the user, which leads to unnecessary waste of network resources. In this paper, we propose a new forwarding strategy named counteracting redundant data (CRD) to reduce the transmission of redundant Data. The CRD strategy introduces a new packet called Data Acknowledgement (DACK) to stop forwarding redundant data. When a router receives a DACK, it will delete the matched Pending Interest Table (PIT) entry with the same name prefix and same incoming interface as the DACK. Thus, subsequent Data will be discarded when the corresponding PIT entry in the router no longer exists. According to the transmission model with tree structure, forwarding number that indicates the number of DACK being forwarded is a very important factor affecting the transmission overhead of CRD strategy. In our simulation, the results show the CRD strategy can improve transmission efficiency, reduce transmission overhead while ensuring a certain reliability, and also decrease the storage of content store at the same time. Copyright © 2015 John Wiley & Sons, Ltd.     

A preload cooperative sensing scheme with low overhead in cognitive radio networks

In cognitive radio networks (CRNs), users can collaborate to improve the accuracy of spectrum sensing, but a large number of secondary users reporting their local sensing results may create significant overhead. In this paper, we propose a new pre‐sensing scheme, called preload cooperative sensing (PCS), which not only attains the given sensing accuracy for CRNs but also reduces the whole sensing time T. In order to reduce the sensing overhead in CRNs, the proposed scheme adopts two key technologies: selective reporting technology and pre‐sensing sequential detection technology. Selective reporting technology implies that only those users, which detect the presence of primary users, need to report the results, while pre‐sensing sequential detection technology is an asynchronous parallel scheme, which sets a threshold to determine the presence of primary users. Considering the preload sensing slots, we derive a formula to express the overall miss detection probability, and at a given Quality of Service (QoS) value, the sensing overheads of PCS are analyzed over Rayleigh fading channel. Also, we consider the overhead minimization problems in PCS. Simulation results show the superiority and efficiency of the PCS scheme. Copyright © 2015 John Wiley & Sons, Ltd.