Performance Bound for LDPC Coded Unitary Space–Time Modulation

This paper is concerned with the bit error probability (BEP) of coded unitary space–time modulation systems based on finite-length low density parity check (LDPC) codes. The union bound on the BEP of the maximum likelihood (ML) decoding is derived for any code rate, unitary space–time constellation and mapping. The tightness of the bound is checked with simulation results of the ordered statistic decoding (OSD). Numerical and simulation results show that the union bound is also close to the error performance of the sum–product (SP) decoding at low BEP levels when Gray mapping is employed. The derived bound is useful to benchmark the error performance of finite-length coded unitary space–time modulation systems, especially for those that employ short-to-medium length LDPC codes.

分布式并行数据挖掘计算框架及其算法研究

为了提供一个灵活可扩展的计算平台进行高效的挖掘计算，提出了一种应用于分布和并行环境的数据挖掘计算框架和相应的算法。通过分析关联规则挖掘理论和以往算法的优缺点，建立一种分布式并行数据挖掘的计算框架，并给出相应的求解算法。实例分析表明该计算框架能够减少节点问的通信开销，保持了良好的可扩展性：挖掘算法则利用本地节点动态有序集合枚举树生成方法代替数据库节省了本地空间的占用．大大提高了查找的计算效率。     

A Comparison of Bit-Parallel and Bit-Serial Architectures for WDM Networks

Wavelength division multiplexing (WDM) is emerging as a viable solution to reduce the electronic processing bottleneck in very high-speed optical networks. A set of parallel and independent channels are created on a single fiber using this technique. Parallel communication utilizing the WDM channels may be accomplished in two ways: (i) bit serial, where each source-destination pair communicates using one wavelength and data are sent serially on this wavelength; and (ii) bit parallel, where each source-destination pair communicates using a subset of channels and data are sent in multiple-bit words. Three architectures are studied in the paper: single-hop bit-serial star, single-hop bit-parallel star, and multi-hop bit-parallel shufflenet. The objective of this paper is to evaluate these architectures with respect to average packet delay, network utilization, and link throughput. It is shown that the Shufflenet offers the lowest latency but suffers from high cost and low link throughput. The star topology with bit-parallel access offers lower latency than the bit-serial star, but is more expensive to implement.     

LTE中卷积码的译码器设计与FPGA实现

基于长期演进（LTE）的Tail—biting卷积码,介绍了维特比译码算法,它是一种最优的卷积码译码算法。由于Tail—biting卷积码的循环特性,采用固定延迟译码的方法,降低了译码复杂度。通过使用全并行的结构及简单的回溯存储方法,设计了一个具有高速和低复杂度的固定延迟译码器。在FPGA上实现并验证,验证结果表明译码器的性能满足了LTE系统的要求。     

UPS双机并联冗佘系统故障处理一则

本结合河北移动通信有限责任公司所用UPS双机并联冗余系统出现不同步报警后的处理过程，主要介绍UPS并联系统故障分析判断的思路、操作处理的方法，以及应注意的事项，以供参考。     

双机并联UPS的使用与维护

主要论述了自控系统采用UPS的必要性，以及SAUCRU PARALLEL SYSTEM(塞里克鲁并联系统)UPS在现场的具体应用。介绍了并联系统UPS的特性及其实现，现场外接旁路的设计与具体操作，以及日常维护中的问题。     

基于并行DSPs的脉冲压缩处理实现

详细阐述了一种基于多DSP信号处理器系统的脉冲压缩算法的并行流水实现方法，包括算法分析／分解、数据流组、多片运算任务分配以及片间同步等内容，并在文末讨论了一些实时系统必须满足的性能要求。该系统对多形式多时宽信号的脉冲压缩主旁瓣比均达30dB以上，具有良好的实用价值。     

A memory efficient parallel layered QC-LDPC decoder for CMMB systems

This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the “one cycle one layer access” timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130 nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29 mm². The total memory bits consumption is only 130.5 K which consumes 2.53 mm² memory area.     

基于MapReduce的海量图像处理模型的研究

针对目前图像的格式和数量都在不断增加,传统的串行处理方法无法满足海量的图像数据处理的问题,提出一种基于MapReduce并行框架的海量图像数据处理模型.模型中取消了Reduce处理函数,在Map函数处理完成后直接输出处理结果,不仅避免了Reduce函数和Re-duce任务处理所需的时间,同时减少了Map与Reduce阶段之间操作所消耗的时间.实验基于Hadoop伪分布式云平台,实现了文中提出的并行处理模型.     

Dynamically scalable dual-core pipelined processor

This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs. This design aimed to be implemented on Xilinx Spartan 3E XC3S500E FPGA.