高精度音频∑-ΔDAC的设计

提出了一种用于音频领域的18 bit∑-ΔDAC设计,其中采样率为48kHz的18bit数据经过插值滤波器的过抽样率为128,∑-Δ调制器选用4阶3bit输出的MASH结构,在Matlab下进行了系统仿真,测试结果表明方案可行.     

COD: Diversity-Adaptive Subspace Processing for Multipath Separation and Signal Recovery

This paper proposes a generalized multipath separability condition for subspace processing and derives a novel COD (Combined Oversampling and Displacement) algorithm to utilize both spatial and temporal diversities for path separation, DOA (Direction of Arrival) estimation and signal recovery. A unique advantage lies in its ability to cope with the situation where the number of multipaths is larger than that of antenna elements, which has not been treated in the traditional approaches. COD strategy solves the antenna deficiency problem by combining vertical expansion with temporal oversampling and horizontal expansion with spatial displacement. We provide a detailed analysis on the theoretical footings for COD factorization and multipath separability conditions, which naturally leads to COD path separation and DOA estimation algorithms. Another advantage of COD factorization hinges upon its ability to generate a multiplicity of eigenvalues which greatly facilitates a SIMO channel equalization formulation useful for signal recovery. This paper also proposes a frequency-domain total-least-square algorithm for SIMO equalization procedure. Finally, simulation results on path separation, DOA estimation and signal recovery are demonstrated.     

Delta-Sigma A/D转换器原理及其PSpice仿真

为了深入理解Delta-Sigma A/D转换器的工作原理,合理地使用这类A/D转换器产品,或者用FPGA实现自己的Delta-Sigma A/D转换器设计。采用PSpice仿真软件进行模拟仿真的方法,对不同幅度的输入信号进行了一阶Delta-Sig-ma A/D转换器仿真实验,获得了与理论相一致的结果。通过对元件的参数扫描仿真为实际电路设计中元件的选择提供了实验依据。仿真实验过程完整,易于重复,与纯数学推导相比,仿真具有直观的特点。     

A 1.8 V 15-bit 1 mW 2nd-Order Sigma-Delta Modulator

Low-voltage low-power sigma-delta modulators provide a critical interface in portable mixed-signal electronic systems. This paper deals with the design andimplementation of a low-voltage, low-power 2nd-ordersigma-delta modulator operating from a single 1.8 V powersupply using a conventional 3.3 V, double-poly, 0.35 mCMOS process, based on fully-differentialswitched-capacitor techniques. All the circuit blocks areintegrated on one chip, and the input common-mode voltageis set at mid-rail, resulting in low power dissipation,minimum off-chip components, and high efficiency,flexibility and compatibility. The design is useful forvoice applications in personal communications systemssupplied by two nickel-cadmium or alkaline batteries. Themodulator exhibits a 15-bit dynamic range for a 7 kHzbandwidth, and a 14-bit dynamic range for a 20 kHzbandwidth at an oversampling frequency of 2.56 MHz. Thepeak SNDR reaches 62 dB. The complete 2nd-order modulatorhas a power dissipation of 0.99 mW, and occupies 0.31mm² die area excluding bonding pads.     

High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a modulator. This design algorithm includes the advantages from both single-bit M and multi-bit M. This paper utilizes a second order lowpass modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.     

An Insider Data Leakage Detection Using One-Hot Encoding,Synthetic Minority Oversampling and Machine Learning Techniques

Insider threats are malicious acts that can be carried out by an authorized employee within an organization. Insider threats represent a major cybersecurity challenge for private and public organizations, as an insider attack can cause extensive damage to organization assets much more than external attacks. Most existing approaches in the field of insider threat focused on detecting general insider attack scenarios. However, insider attacks can be carried out in different ways, and the most dangerous one is a data leakage attack that can be executed by a malicious insider before his/her leaving an organization. This paper proposes a machine learning-based model for detecting such serious insider threat incidents. The proposed model addresses the possible bias of detection results that can occur due to an inappropriate encoding process by employing the feature scaling and one-hot encoding techniques. Furthermore, the imbalance issue of the utilized dataset is also addressed utilizing the synthetic minority oversampling technique (SMOTE). Well known machine learning algorithms are employed to detect the most accurate classifier that can detect data leakage events executed by malicious insiders during the sensitive period before they leave an organization. We provide a proof of concept for our model by applying it on CMU-CERT Insider Threat Dataset and comparing its performance with the ground truth. The experimental results show that our model detects insider data leakage events with an AUC-ROC value of 0.99, outperforming the existing approaches that are validated on the same dataset. The proposed model provides effective methods to address possible bias and class imbalance issues for the aim of devising an effective insider data leakage detection system.     

基于Σ-Δ型ADC的过采样应用

本文讨论了基于高分辨精度的24位∑-△ ADC（AD7760）的过采样应用设计,验证了针对白噪声下的微弱信号,采用过采样技术可以提高ADC的精度和信噪比。     

基于FPGA的异步LVDS过采样的研究和实现

针对LVDS接口,研究并实现了一种基于FPGA的LVDS过采样技术,重点对LVDS过采样技术中系统组成、ISERDESE2、时钟采样、数据恢复单元、时钟同步状态机等关键技术进行了描述,并基于Xilinx FPGA进行了验证,传输速率达到了1.25Gbps。文章的研究为基于FPGA实现系统之间的高速互连具有一定的工程参考价值。     

短波射频数字化接收机的设计与实现

针对传统中频数字化接收机复杂度高、灵活性差等问题,设计并实现了一种新型短波射频数字化接收机.该接收机由A/D、数字下变频器(DDC)、DSP、D/A、CPLD等几部分组成,实现了短波信号的射频数字化处理.详细介绍了接收机的设计方案,并对常见的调幅(AM)、等幅报(CW)、单边带(ISB)等信号进行了接收测试.在输入电平为-103～0 dB动态范围内,解调输出质量都能达到12 dB左右信纳得(SND).     

Cell search algorithms for the 3G long-term evolution

This article presents downlink initial synchronization and cell identification algorithms for long term evolution (LTE) of third-generation (3G) mobile communication systems, which are based on synchronization channel (SCH) and cell specific pilot symbols, respectively. The key features of the proposed scheme are: it can improve performance of the frequency synchronization through oversampling of the SCH, it can support a large number of target cells by modulating a cell-specific pilot sequence over two symbols within a subframe, and it can guarantee cell identification performance by maximally ratio combining the frequency domain differential cross-correlation. Simulations show that the proposed scheme has a potential use in 3G LTE.