放射状双pn结抑制片上电感衬底损耗

使用标准CMOS工艺,在放射状的n阱上面扩散p+,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗.提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度.首次通过接地的p+扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点.从LC振荡器的模型出发,研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响.给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

低损耗衬底上实现无源低通滤波器

分析比较了不同种类衬底上无源器件(片上电感和电容)的损耗机理,在OPS(氧化多孔硅)和HR(高阻硅)低损耗衬底上分别实现了片上低通滤波器.为了研究衬底损耗,设计了平面螺旋电感,其Q值在两种衬底上的仿真结果都超过了20.在OPS衬底上的低通滤波器实测-3dB带宽为2.9GHz,通带插入损耗在500MHz为0.87dB;在HR衬底上的低通滤波器实测-3dB带宽为2.3GHz,通带插入损耗在500MHz为0.42dB.     

基于嵌套循环指令分析的片上存储器分配策略

本文提出了一种无Cache情况下基于嵌套循环指令分析的片上存储器(On-chip memory)分配策略.该策略分析程序中循环指令,控制划分粒度将所有函数切割成块,然后使用背包算法和优先级算法组合的分配算法,选择合适块放入片上存储器,达到优化程序性能的目的.实验结果表明,该策略能够显著提高程序性能,平均提高一倍,甚至更高,同时它能够预知优化后程序执行时间的变化,最高误差为2%.     

用于无线互连的片上天线金属干扰分析与设计规则

定性分析了金属互连线、电源网格、散热与封装以及金属Dummy Fills对2 mm长、30 μm宽的片上偶极天线对工作特性的影响.通过在硅衬底和散热金属之间引入0.35 mm厚的金刚石介质材料使天线的传输增益在20 GHz时提高了9 dB.为研究这些金属结构和布局对集成偶极天线对的传输增益、相位、阻抗及辐射特性带来的干...     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

一种片上变压器为负载的用于0.13 μm CMOS工艺2.4GHz WLAN的接收机射频前端电路

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μ m CMOS technology, it occupies a 0.612 mm² die size.     

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.     

CCD片上放大器直流输出电压影响因素分析

对电荷耦合器件(CCD)片上放大器直流输出电压的主要影响因素进行了研究,通过对不同源漏工艺、不同栅下注入剂量工艺条件对直流输出的影响分析,指出有效沟道长度和放大管栅下注入是CCD片上放大器直流输出电压的主要影响因素。