A single-inductor dual-output switching converter with average current mode control

are about 40 mV at an oscillator frequency of 600 kHz.     

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

The current network-on-chip (NoC) topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh (S-Mesh). S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks: datapath network (DN) and control network (CN). The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Torus Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%--7%, and the power dissipation is decreased by approximate 2%.     

基于片上肖特基二极管的高功率三倍频器设计

提出了一种基于片上集成电容工艺和带阻滤波结构的高功率三倍频器设计方法。在倍频器输入端,首先对倍频器二极管的直流偏置馈电部分进行改进,在梁式引线结构基础上结合二氧化硅（S_iO₂）工艺实现了片上集成电容,同时解决了三倍频器的直流馈电和射频接地问题,实现电路功能集成的同时也提高了模型仿真精度。此外,在二极管的输入端采用带阻滤波器结构替代传统的低通滤波结构,在保证倍频器性能的同时进一步简化倍频器结构复杂度和尺寸。为进行验证,设计并加工测试了两款中心频率分别为110 GHz和220 GHz的双路功率合成三倍频器。实际测试结果表明,在输入功率500 mW条件下,110 GHz三倍频器的输出峰值功率达到了140 mW,峰值效率接近30%,带宽超过15 GHz;在输入功率300 mW条件下,220 GHz三倍频器的输出峰值功率达到了45 mW,峰值效率达到15%,带宽为15 GHz。两款倍频的测试结果均有优秀表现,验证了设计方法的有效性。     

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.     

Misalignment-aware energy modeling of narrow buses for data encoding schemes

A precise high-level energy model is required for the development and efficiency characterization of on-chip low-power coding and stochastic techniques. The misalignment effect, that is the variation in the delay of the transmitted signals, is conventionally overlooked. This work presents the first high-level misalignment-aware energy model for narrow multi-segment global interconnects. The proposed model has been experimentally validated using a commercial [65]nm technology. Results show a significant improvement in the accuracy of the energy estimation. For instance, the normalized mean square error of the standard model, 8.293%, is reduced to 0.998% by the proposed approach for a typical structure of a 5-wire bus. Furthermore, a case study is used to assess the proposed model using classical bus invert and full invert low-power coding schemes.     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

可重用片上仿真调试协议结构

提出了一种可重用片上仿真调试协议结构,基于此结构设计实现的片上仿真调试逻辑,简单高效,便于重用于新的芯片和新的体系结构.     

基于IP的系统芯片(SOC)设计

随着集成电路设计与工艺技术水平的提高，出现了系统芯片(SOC)的概念。本文介绍了基于IP的SOC设计方式的设计流程，指出了其与传统IC设计方法的不同。讨论了支持SOC设计的几种关键技术，并对SOC的技术优势及发展趋势作了全面阐述。     

An analog feed-forward neural network with on-chip learning

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2 CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.