基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

WiNoC中无线节点和无线链路级拥塞避免的高效路由器设计

无线片上网络中,无线网络拥塞可以分为无线节点级的拥塞和无线链路级的拥塞,这两种拥塞都会造成网络性能下降.针对无线节点和无线链路级拥塞,本文设计了一种拥塞避免的高效无线路由器,首先提出了节点级的拥塞避免机制,无线节点通过广播本地拥塞信息相互感知拥塞程度,避免向拥塞程度较高的无线节点发送数据包;其次提出了链路级拥塞避免机制,在无线接口中设计了并行FIFO,允许无线接口以流水的方式,在单个时钟周期内传输一个拥塞信息数据包和三个数据微片,数学建模证明使用并行FIFO至少降低50%无线信道竞争频率,从而避免了无线链路级拥塞,提高了无线资源利用率.实验表明本文方案相较普通无线路由器增加了少量的面积,但是在网络整体性能、无线路由器性能以及功耗方面都取得了不错的优势.     

单片集成直流-直流转换器的效率提高方法

采用SMIC 0.13μm CMOS工艺,设计实现了开关频率达到250 MHz,单片集成的降压型电源转换器。为了提高电源转换效率,该转换器中的片上电感采用非对称性设计方法,提高了电感的品质因数。采用了高密度片上滤波电容来稳定输出电压,同时对单位电容尺寸的优化设计减小了电容的等效串联电阻以及输出电压纹波。测试结果表明,芯片输入电压为3.3 V,当输出2.5 V电压时,峰值效率达到了80%,最大输出电流达到270 mA;当输出1.8 V电压时,峰值效率达到了70%,最大输出电流达到400 mA。     

片上集成电路系统测试的新电路设计

It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.     

基于IP的系统芯片(SOC)设计

随着集成电路设计与工艺技术水平的提高，出现了系统芯片(SOC)的概念。本文介绍了基于IP的SOC设计方式的设计流程，指出了其与传统IC设计方法的不同。讨论了支持SOC设计的几种关键技术，并对SOC的技术优势及发展趋势作了全面阐述。     

基于片上微腔自反馈注入锁定的窄线宽激光器

对半导体激光器外腔自反馈注入锁定进行了理论分析,研究了片上微腔的自反馈注入锁定对于分布反馈(DFB)激光器输出线宽的影响,分析了决定锁定带宽及线宽压缩系数的关键参数。基于Q值为2.4×10⁶的片上Si₃N₄微腔的后向瑞利散射实现了DFB激光器的自反馈注入锁定,将其输出线宽由自由运转时的556.71 kHz压窄到了92.28 kHz,锁定带宽达到425 MHz。研究结果有助于理解半导体激光器自反馈注入锁定机理,并为实现窄线宽激光器提供了新的结构更简单、集成化潜力更高的方案。     

应用于前端读出电路的片上LDO设计

为满足辐射探测器前端读出电路对模拟电路稳压器片上集成和快速瞬态时间响应的需求,设计了一种基于0.18μm CMOS工艺的全片上集成LDO。采用大摆幅高增益放大器驱动输出功率管,增大了功率管栅极调节电压摆幅,减小了功率管尺寸和LDO压差电压。该放大器同时增大了LDO的环路增益和对功率管栅极的充放电电流,从而改善了瞬态响应性能。为了不牺牲环路增益带宽和芯片面积,并且保证LDO在整个负载电流区间内保持稳定,提出了一种负载电流分区频率补偿方法。仿真结果表明,在负载电容为200 nF,负载电流范围为0～200 mA时,设计的LDO相位裕度均大于53^o。在相同功率管尺寸情况下,采用大摆幅高增益放大器可以将LDO最大输出电流能力提高到两倍以上。当负载电流从10 mA跳变到200 mA时,LDO输出电压恢复时间小于6.5μs。设计的LDO电路面积为120μm×264μm,满载时电源效率为97.76%,最小压差电压为50 mV。     

面向片上光互连的无源H树网络设计

传统的片上电互连已无法满足多核处理系统日益 增长的通信需求,在延迟、能耗和 带宽方面更具优势的片上光互连逐渐引起关注。为了降低片上光网络(optical network-on-chip,ONoC)硬件开销和提升光网络 性能,本文提出一种基于微环谐振器的16端口无源H树光互连网络。利用宽带微环谐振器设 计4组转向光路由器,降低微环谐振器使用并完成端口选择,将信号传输到8端口接收光路由 器以及3级和4级光开关来满足信号的无争用传输。实验结果表明,在16×16阵列规模下与 Crossbar、λ-Router、GWOR、LACE、Light等无源网络结 构相比,无源光H树网络仅需使用 72个微环谐振器。网络平均插入损耗1.49 dB,与λ-Router、GWOR 、TAONoC相比分别降低 了21.5%、10.7%、59.7 %,各路径平均信噪比 为17.48 dB,与λ-Router、GWOR、Light相比分别提高了38.5%、36.0%、17.1%。     

An analog feed-forward neural network with on-chip learning

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2 CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.     

A Distributed Capacitance Analysis of Co-Planar Inductors for a CMOS QVCO with Varactor Tuned Buffer Stage

A quadrature voltage controlled oscillator (QVCO) topology exhibiting low power consumption and high phase noise performance at low supply voltages is presented. The QVCO buffer includes varactors to maximize the output voltage and minimize the current consumption. Microstrip theory and the principle of conservation of energy have been used to evaluate the distributed capacitances of symmetrical inductors to better predict the resonance frequency. The QVCO is implemented in a 0.25 m CMOS process from Agere Systems. The total current consumption including the buffer is 5.4 mA at 1.3 V supply, where of the QVCO uses 2.0 mA. The phase noise measures below –138 dBc/Hz at 3 MHz offset frequency over the 8.9% tuning range 1.715 GHz– 1.875 GHz.Niklas Troedsson (SM98) received the M.Sc. degree in electrical engineering in 2001, and the licentiate degree in circuit design in 2003, both from Lund University, Lund, Sweden. He is currently working towards the Ph.D. degree within the Department of Electroscience, Lund University, Sweden. His research interests include low voltage RF CMOS, integrated quadrature oscillators, and monolithic inductors.Henrik Sjöland (M98) received the M.Sc. degree in electrical engineering in 1994, and the Ph.D. degree in applied electronics in 1997, both from Lund University, Lund, Sweden. In 1999, he spent one year visiting the Abidi group at UCLA, Los Angeles, CA, as a Fulbright postdoctoral scholar. He is currently an associate professor at Lund University, Lund, Sweden. His research interests include the design and analysis of analog integrated circuits, feedback amplifiers, and RF CMOS. Dr. Sjöland is the author of Highly Linear Integrated Wideband Amplifiers (Kluwer, Boston, MA: 1999).