All-In-One Hardware Devices with Event-Based Vision Sensor Arrays for Image Sensing,Computing, and Learning

Metal oxide semiconductors (MOSs) are considered as potential candidates for the low-cost, large-area fabrication of flexible optoelectronic devices. However, the current optoelectronic devices based on MOSs are limited to unidirectional photoresponse, which constrains the performance of MOSs-based vision sensors for artificial vision systems. Herein, for the first time, a flexible artificial vision system integrated with optical perception, computation, and learning functionalities is demonstrated using SnO optoelectronic synaptic transistor-based event-driven vision sensors to enable dynamic image perception, noise reduction, detection, and recognition. Specifically, an ambipolar SnO transistor is demonstrated by introducing HfO₂ passivation layer, which facilitates the movement of O atoms around Sn-vacancy sites to the HfO₂ layer to achieve the transformation from p-type to ambipolar transport behaviors. More importantly, the HfO₂-passivated SnO transistors exhibit gate-tunable bidirectional photoresponse behavior, which is essential to simulate the neurobiological functionalities of bipolar cells. This way, the multilayer neural network learning circuit built from SnO transistors achieves fast recognition at a 16% Gaussian noise level and high recognition accuracy up to 95.2% for pattern letters. Under the bending states, recognition accuracies are still retained at 91.2%. These properties are well retained even under the influence of 100% offset of the synaptic programming value.     

2.5GHz低相位噪声CMOS LC VCO的设计

用0.35μm、一层多晶、四层金属、3.3V的标准全数字CMOS工艺设计了一个全集成的2.5GHz LC VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件1/f噪声的影响.为了减少高频噪声的影响,采用了在片LC滤波技术.可变电容采用增强型MOS可变电容,取得了23%的频率调节范围.采用单个16边形的对称片上螺旋电感,并在电感下加接地屏蔽层,从而减少芯片面积,优化Q值.取得了在离中心频率1MHz处-118dBc/Hz的相位噪声性能.电源电压为3.3V时的功耗为4mA.     

Automatic Window Repositioning Technique for Digital Window Comparator Used Within Mixed-Signal Design-for Testability Schemes

The construction of digital window comparators for the on-chip evaluation of analogue signals within the mixed-signal integrated circuit is reviewed. One of the difficulties in their application is due to the lot-to-lot variation of the comparator window. A technique that allows the automatic window repositioning is described by which the window shift can be compensated. For this automatic compensation a so-called reference comparator is required. From the reference comparator the control signal are derived to select the actual configuration of the used evaluation comparators. It is shown, that this technique allows the automatic lot condition adjustment of the evaluation comparators by repositioning the windows of those comparators. As a synergy effect this technique provides lot specific information for an automated test equipment that can be documented in the test results for further diagnosis and traceability capabilities.Daniela De Venuto received the master degree in 1989 in Electronic Engineering at the Politecnico di Bari, Italy. In 1992 she obtained the Ph.D. degree for a thesis entitled: Fault diagnosis in digital integrated circuits by pulsed electron beam. In 1994 Dr. De Venuto took a post-doctoral position at the Politecnico di Bari. She became assistant professor in 1995 at the University of Lecce, Italy. Currently she is professor of Electronics at the Politecnico di Bari, Italy, teaching courses in Automatic Design of Integrated Circuits and Systems and Analog Electronics.In 2000 she was on sabbatical leave at the Laboratoire dElectronique Generale at the EPFL in Lausanne, Switzerland. During this stay she worked in the area of Hall sensor interface design in SOI technology. Actually she is visiting lecturer at the Centre for Microsystems Engineering, University of Lancaster, UK, where she started a collaboration on the design and test and design for testability of delta sigma converter. Since 2003 she is also Visiting Scholar at the University of Washington (Seattle). She is member of National Institute of Nuclear Physics (INFN) and she is also involved in CERN (Geneva, Switzerland) project, for test of radiation hardened analogue front-ends of pixel-detector. She is IEEE member and also member of the Editorial Board of Microelctronics Journal. Her research interests include the design and test of analogue ICs, design for testability for analogue and mixed-signal circuits as well as silicon solid-state detector design and characterisation.Michael J. Ohletz graduated in high frequency electrical engineering at the Fachhochschule Osnabrück, Germany, in 1977 and at the University of Hannover, Germany, in 1982. From 1982–1983 he was working at the cooperate research and development centre of Siemens AG in Munich, Germany. Between 1983– 1989 he was research assistant at the Institute for Electrodynamics at the University of Hannover where he received the Dr.-Ing. degree (PhD) for a thesis about the Hybrid Built-In Self-Test (HBIST) for mixed-signal ICs. Since 1989 Dr. Ohletz was project manager at the Information Technology Lab, and head of the analogue and mixed-signal design&test group. In 1998 he joined the R&D staff of Alcatel Microelectronics in Brussels, Belgium, as project and design methodology leader for high-voltage, mixed-signal ASICs for industrial and automotive applications. Between 2000 and 2002 he was program manager for automotive products. Currently Dr. Ohletz is manager for the whole program management of all mixed-signal ASIC products in Europe including automotive, industrial and computer/ consumer ASIC products at AMI Semiconductor in Vilvoorde, Belgium. His research interests include design, test and design methodology of high-voltage integrated mixed-signal circuits. In particular his interest is on automotive sensor applications. Beside this Dr. Ohletz serves as a reviewer for various international journals, conferences and workshops. He also is a peer referee for different national research councils in Europe and North America as well as for the Commission of the European Union.Bruno Riccò was born in Parma (Italy) on February 8, 1947. In 1971 he graduated in electrical engineering at the University of Bologna (Italy) and in 1975 received a Ph.D. from the University of Cambridge (U.K.) where he worked at the Cavendish Laboratory. In 1980 he became Full Professor of Applied Electronics at the University of Padua (Italy) and in 1983 he joined the University of Bologna (Italy). Since 1978 he has been holding courses on Electron Devices, Digital Integrated Electronics, Semiconductor Technology, IC Reliability and Testing. He has been Visiting Professor at the University of Stanford, at the IBM Thomas J. Watson Research Center (Yorktown Heights) and at the University of Washington. From 1986 to 1996 he has been European Editor of the IEEE Transaction on Electron Devices. Nominated Senior Member of the IEEE in 1991, 1n 1995 he received the G. Marconi Award by the Italian Association of Electrical and Electronics Engineers (AEI), for his research in electronics. In 1996 he became President of the Group of Electron Devices, Technologies and Circuits of AEI and in 1998 became President of the Italian Group of Electronics Engineers. In 1999 he was appointed European representative for the International Electron Device Meeting (IEDM). In 2000 he has become Vice-President of the North Italy Section of IEEE. In 1999 he has founded the first university spin-off in Italy working in the field of advanced digital systems. Prof. Ricco has been consulting for major semiconductor companies and for the Commission of the European Union in the definition, evaluation and review of research projects in microelectronics. Form a scientific point of view, Prof. Ricco has worked in the field of solid-state devices and ICs. In particular, he has made many contributions to the understanding and modeling of electron transport, tunneling in thin insulating films, silicon dioxide physics, MOSFETs physics, latch-up in CMOS structures, device modeling and simulation. He is currently working also in the field of IC design, evaluation and testing. Prof. Ricco is (co-) author of over 270 publications, more than half of which have published on major international Journals, of three books and of 6 patents in the field of Non-Volatile memories.     

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Recent advances in Deep Submicron (DSM) design and manufacturing technologies have brought to the forefront the importance of inductive coupling amongst long interconnect in high performance microprocessors. Inductive coupling has been shown to depend directly on the overlap length between adjacent signal wires, the activity on these wires and the distance separating them. This paper presents a technique—known as swizzling—that exploits the inductive coupling dependence on distance to reduce the effect of any particular attacker on any of its victims. In the swizzling technique, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other. This paper shows that this technique significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.Bassel Soudan (S89, M94) received his B.Sc. degree in Electrical Engineering with highest honors from the Department of Electrical Engineering and Computer Science at the University of Illinois at Chicago in 1986. He received his M.Sc. and Ph.D. degrees in 1988 and 1994 respectively from the Department of Electrical and Computer Engineering at the Illinois Institute of Technology.From 1994 through 1996, he was with Design Technology group at Intel Corporation in Hillsboro Oregon where he was involved in the development of Intels Athena suite of EDA CAD tools. He was particularly involved with the design of full chip layout tools and then the verification and validation effort of the suite. From 1996 through 1999, he was with the Merced Microprocessor Design Team at Intel in Santa Clara California. He was a member of the Full-Chip Layout Design Automation team responsible for developing, maintaining, and supporting the suite of full chip layout tools utilized by the project. In the last six months of the project, he was part of the team responsible for assembling and verifying the design. Since 1999, he is an assistant professor at the Department of Electrical/Electronics and Computer Engineering at the University of Sharjah in the United Arab Emirates. His primary research interests include interconnect design, high performance computer architecture and design of new EDA tools and methodologies.He is a member of the IEEE, the IEEE Circuits and Systems Society, the IEEE Computer Society, the ACM, the ACM Special Interest Group on Design Automation, and the ACM Special Interest Group on Microarchitecture.     

对两种不同的低噪声放大器优化方法的讨论和比较

摘要：本文介绍并且比较了两种不同的低噪声放大器设计方法,即经典二端口方法和Shaeffer所提出的方法,并且最后分别运用这两种方法设计不同版本的低噪声放大器。对它们的优点和缺点也进行了讨论。本文主要研究对象为前一种技术的理论推导,因为该技术在以往的文献中极少有介绍。另外,以往的大部分优化方法均忽略了一个晶体管的寄生电容,因为本文在小信号模型中的计算中加入了该寄生电容,所以大大减少了计算误差,使得模型能够较准确的预测仿真结果。使用前一种方法,本文设计了一个2.4GHz的全集成低噪声放大器,在1.3mA的电流约束下实现了仅为1.4dB的噪声系数。另外,本文也利用后一种方法设计了另一个版本,该低噪声放大器已经投入流片并已测试。     

芯片内/间无线互连技术发展综述

为了解决超大规模集成电路布线复杂的问题,无线互连技术(WIT)应运而生。介绍了实现芯片内/间无线互连的两类技术,一类是基于片上天线的无线互连技术,另一类是基于AC耦合的无线互连技术。从实现成本、功耗,传输性能方面对这两类技术进行了分析与比较,讨论了它们的具体应用及适用范围,同时也总结了两者目前存在的问题,并指出了其未来的研究方向,对今后芯片内/间无线互连技术的应用研究具有一定的参考意义。     

使用小片上电容的VCCS补偿的LDO

A stable LDO using VCCS(voltage control current source) is presented.The LDO is designed and implemented on GF 2P4 M 0.35 m CMOS technology.Compared with a previous compensation scheme,VCCS can implement a real stable LDO with a small on-chip capacitor of 1 p F,whose stability is not affected by the variable ESR(equivalent series resistance) of the output capacitor.The unit gain frequency of the LDO loop can achieve 1.5 MHz,improving the transient response.The PSR of the LDO is larger than 45 d B within 0–40 k Hz.The static current of the LDO at heavy load of 100 m A is 57 A and the dropout voltage of the LDO is 150 m V.Experimental results show that a setting time of 10 s is achieved,and the variation of output voltage is smaller than 35 m V for a 100 m A load step in transient response of the LDO.     

一种高效率绿色模式开关电源控制器的研究

提出了一种高效率绿色模式降压型开关电源控制器芯片的设计,特点是采用PWM/Burst多模式控制策略提高全负载条件下的电源转换效率.由于降低了低负载和待机条件下的电源功耗,可减小由电池供电的现代便携式设备的静态功耗,延长设备的待机时间和电池的寿命.芯片还实现了模式转换过程中的平滑过渡以及过冲电压的抑制.此外,还引入一种高精度、高效率的片上电流榆测技术,进一步降低了功耗.该芯片在1.5μm BcD(bipolar-cMOS-DMOS)工艺下设计和制造,测试结果表明芯片已达到预期的性能要求.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

A full on-chip CMOS low-dropout(LDO) voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area...