低损耗衬底上实现无源低通滤波器

分析比较了不同种类衬底上无源器件(片上电感和电容)的损耗机理,在OPS(氧化多孔硅)和HR(高阻硅)低损耗衬底上分别实现了片上低通滤波器.为了研究衬底损耗,设计了平面螺旋电感,其Q值在两种衬底上的仿真结果都超过了20.在OPS衬底上的低通滤波器实测-3dB带宽为2.9GHz,通带插入损耗在500MHz为0.87dB;在HR衬底上的低通滤波器实测-3dB带宽为2.3GHz,通带插入损耗在500MHz为0.42dB.     

力学加载实验的微小压力测量控制的装置研究

在一些生物实验中，需要对培养细胞的琼脂施加一个恒定的微小压力，以保持细胞的活性。为此，研制了一种用于植物细胞力学加载实验的微小压力测量控制的装置，该文系统地介绍了该测量的结构及控制系统的设计。实验结果表明，该装置达到预期效果，值得推广应用。     

Design of 1.9 GHz RF CMOS VCO

A voltage controlled oscillator (VCO) module is designed, which can be used for the third generation mobile communication (3G) system. The circuit is simulated by spectre radio frequency (RF) by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows: tuning range 1.804 GHz-2.039 GHz, phase noise - 136.457 dBc/Hz @1 MHz, - 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V-2.6 V, power consumption 25 mW. The layout of the related circuit is drawn by the Virtuoso Layout Editor.     

基于FPGA的差分信号阻抗匹配研究

为了节约PCB板空间,充分灵活利用FPGA内部资源,对FPGA内置差分信号匹配终端进行研究。根据差分信号阻抗匹配的基础理论,在自制的PCB电路板上利用差分信号线传递时钟和图像数据。在FPGA内设置不同类型的片内匹配终端,通过示波器观察时钟、图像数据,利用Visual DSP＋＋软件自带的Image Viewer功能观察图像。结果表明,使用片内匹配终端不会恶化差分信号,并能大大节省PCB板空间,且终端匹配更灵活。     

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Recent advances in Deep Submicron (DSM) design and manufacturing technologies have brought to the forefront the importance of inductive coupling amongst long interconnect in high performance microprocessors. Inductive coupling has been shown to depend directly on the overlap length between adjacent signal wires, the activity on these wires and the distance separating them. This paper presents a technique—known as swizzling—that exploits the inductive coupling dependence on distance to reduce the effect of any particular attacker on any of its victims. In the swizzling technique, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other. This paper shows that this technique significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.Bassel Soudan (S89, M94) received his B.Sc. degree in Electrical Engineering with highest honors from the Department of Electrical Engineering and Computer Science at the University of Illinois at Chicago in 1986. He received his M.Sc. and Ph.D. degrees in 1988 and 1994 respectively from the Department of Electrical and Computer Engineering at the Illinois Institute of Technology.From 1994 through 1996, he was with Design Technology group at Intel Corporation in Hillsboro Oregon where he was involved in the development of Intels Athena suite of EDA CAD tools. He was particularly involved with the design of full chip layout tools and then the verification and validation effort of the suite. From 1996 through 1999, he was with the Merced Microprocessor Design Team at Intel in Santa Clara California. He was a member of the Full-Chip Layout Design Automation team responsible for developing, maintaining, and supporting the suite of full chip layout tools utilized by the project. In the last six months of the project, he was part of the team responsible for assembling and verifying the design. Since 1999, he is an assistant professor at the Department of Electrical/Electronics and Computer Engineering at the University of Sharjah in the United Arab Emirates. His primary research interests include interconnect design, high performance computer architecture and design of new EDA tools and methodologies.He is a member of the IEEE, the IEEE Circuits and Systems Society, the IEEE Computer Society, the ACM, the ACM Special Interest Group on Design Automation, and the ACM Special Interest Group on Microarchitecture.     

Biologically-Inspired On-Chip Learning in Pulsed Neural Networks

Self-learning chips to implement many popular ANN (artificial neural network) algorithms are very difficult to design. We explain why this is so and say what lessons previous work teaches us in the design of self-learning systems. We offer a contribution to the biologically-inspired approach, explaining what we mean by this term and providing an example of a robust, self-learning design that can solve simple classical-conditioning tasks. We give details of the design of individual circuits to perform component functions, which can then be combined into a network to solve the task. We argue that useful conclusions as to the future of on-chip learning can be drawn from this work.     

微电子封装技术的新趋势

本文从应用的观点出发简要介绍了各种封装技术在新世纪中的发展趋势。论述了如CSP、BGA 及倒装芯片等先进封装技术在微电子工业中所发挥的重要作用。     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

一种CMOS单片LDO线性稳压器的设计

提出了一种单片集成的高电源抑制比LDO线性稳压器,主要应用于PLL中VCO和电荷泵的电源供给.该稳压器采用RC补偿方案,与其他补偿方法相比,RC补偿几乎不消耗额外电流.误差放大器采用折叠共源共栅结构,可以提供较高的电源抑制比,并且使得设计的LDO为两级放大器结构,有利于简化补偿网络.所设计的LDO在低频时电源抑制比(PSR)为一69 dB,在lMHz处的电源抑制比为-19 dB.采用0.35 μm工艺流片,测试结果表明,该LDO可以为负载提供70 mA的电流.     

双通道流水线Flash存储系统的设计

提出了一种新颖的基于NAND Flash的存储系统.采用了双通道和流水线设计,提高了存储系统的吞吐量、降低平均响应时间.片上缓存技术隐藏了Flash的操作延时,提高了数据存储的速度.相比较传统的设计,平均读速度提高了约70.3%,平均写速度提高了约79.7%.