太赫兹片上系统和基于微纳结构的太赫兹超宽谱源的研究进展

目前太赫兹辐射信号的功率不高,辐射带宽也较窄,这些对于生物化学、含能材料的太赫兹检测应用领域来说是一大限制因素,因此如何获得宽谱高功率的太赫兹源对于太赫兹时域光谱系统的发展是非常重要的;另一方面,常规的太赫兹系统是在自由空间传输探测的,测量过程需要在氮气或者干燥空气环境中进行,以克服空气中水的吸收干扰,同时自由空间中的光场与物质相互作用的模式又降低了物质检测的灵敏度,这对于痕量物质检测来说构成了挑战.面对这一问题,太赫兹片上系统利用微纳结构中的局域场效应实现对物质的低浓度检测,此方案有助于解决这一应用难题.综上所述,本文分成以下两部分阐述:首先阐述了纳米金属薄膜作为新的太赫兹源,它可以同时产生非相干的和相干的太赫兹信号,其输出为超过100 THz的太赫兹-红外辐射,功率高达10 mW,这种超宽谱和高功率现象主要是由于非相干的热辐射效应引起的;第二,阐述了基于不同传输线结构、不同基底材料的太赫兹片上系统结构设计和光谱应用.基于共面带状线结构和聚合物材料基底的太赫兹片上系统有着较低的损耗,能够实现超过2 THz带宽的测量和生物化学应用.     

一种采用斩波稳零技术的16位,96kHz带宽Σ-Δ AD转换器

介绍了一个16位精度Σ-Δ型模拟数字转换器.它由一个模拟的调制器和一个数字降采样滤波器组成.调制器采用了传统的单环两阶的结构,在第一阶调制器中采用了斩波稳零技术来消除电路的闪烁噪声.数字的降采样器包括多相梳状滤波器和波数字滤波器,功耗低,面积小.实验结果表明转换器获得了92dB的动态范围和96kHz的带宽.整个芯片由0.18μm六层金属CMOS工艺制造,芯片面积为2.68mm2,功率消耗仅为15.5mW.     

32位ARM内核微处理器W90N740及其应用

在对ARM体系结构进行分析的基础上 ,介绍了32位ARM核处理器W90N740的结构特点和优异性能 ,讨论了它的应用方法。给出了用W90N740芯片降低系统成本的实现方案     

Experimental Characterization of On-Chip Single and Double-Coupling Spiral Inductors

Experimental investigations on on-chip single and double-coupling square spiral inductors on silicon substrate are performed. For each pair of double-coupling inductors, they have the same edge distance, but with different turn numbers. Based on the measured S-parameters using de-embedding procedure, the inductance and Q-factor of the single square inductor are examined at first, and good agreement is obtained in the extracted inductance, compared to the predicted values using a closed-form series inductance equation. While for double-coupling spiral inductors, the smaller the product of two turn numbers, the weaker coupling will be, and in particular at low frequencies.     

单片集成直流-直流转换器的效率提高方法

采用SMIC 0.13μm CMOS工艺,设计实现了开关频率达到250 MHz,单片集成的降压型电源转换器。为了提高电源转换效率,该转换器中的片上电感采用非对称性设计方法,提高了电感的品质因数。采用了高密度片上滤波电容来稳定输出电压,同时对单位电容尺寸的优化设计减小了电容的等效串联电阻以及输出电压纹波。测试结果表明,芯片输入电压为3.3 V,当输出2.5 V电压时,峰值效率达到了80%,最大输出电流达到270 mA;当输出1.8 V电压时,峰值效率达到了70%,最大输出电流达到400 mA。     

一种CMOS单片LDO线性稳压器的设计

提出了一种单片集成的高电源抑制比LDO线性稳压器,主要应用于PLL中VCO和电荷泵的电源供给.该稳压器采用RC补偿方案,与其他补偿方法相比,RC补偿几乎不消耗额外电流.误差放大器采用折叠共源共栅结构,可以提供较高的电源抑制比,并且使得设计的LDO为两级放大器结构,有利于简化补偿网络.所设计的LDO在低频时电源抑制比(PSR)为一69 dB,在lMHz处的电源抑制比为-19 dB.采用0.35 μm工艺流片,测试结果表明,该LDO可以为负载提供70 mA的电流.     

A new FIFO for transferring data between two unrelated clock domains

A new simple-to-design FIFO that allows data transfer between two clock domains of unrelated frequencies has been developed. The fully synchronous interfaces significantly ease the system-on-chip integration process. With a relatively low gate count, the proposed FIFO allows the producer and consumer to put/get data at their respective frequencies (1?datum/clock cycle) till it gets filled, then the rates converge to the lower of the two frequencies. The maximum initial latency is three cycles of the consumer's clock. Several manifestations of the FIFO have been developed for different design cases including producer/consumer data width mismatch. Operation of the FIFO has been verified using both gate-level simulations and SPICE simulations with a 0.13?µm, 1.2?V technology. An 8-cell FIFO showed proper operation at producer and consumer clock frequencies of 2 and 3.125?GHz, respectively, with a data transfer rate of more than 2?giga datum/s and an average power of 721?µW.     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

片上集成电路系统测试的新电路设计

It is very important to detect transition-delay faults and stuck-at faults in system on chip （SoC） under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock （OCC） controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation （ATPG） tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.