Multi-level non-volatile organic transistor-based memory using lithium-ion-encapsulated fullerene as a charge trapping layer

We report on multi-level non-volatile organic transistor-based memory using pentacene semiconductor and a lithium-ion-encapsulated fullerene (Li⁺@C₆₀) as a charge trapping layer. Memory organic field-effect transistors (OFETs) with a Si⁺⁺/SiO₂/Li⁺@C₆₀/Cytop/Pentacene/Cu structure exhibited a performance of p-type transistor with a threshold voltage (V_th) of −5.98 V and a mobility (μ) of 0.84 cm² V⁻¹ s⁻¹. The multi-level memory OFETs exhibited memory windows (ΔV_th) of approximate 10 V, 16 V, and 32 V, with a programming gate voltage of 150 V for 0.5 s, 5 s, and 50 s, and an erasing gate voltage of −150 V for 0.17 s, 1.7 s, and 17 s, respectively. Four logic states were clearly distinguishable in our multi-level memory, and its data could be programmed or erased many times. The multi-level memory effect in our OFETs is ascribed to the electron-trapping ability of the Li⁺@C₆₀ layer.     

Comparison of Operating Mechanisms for the Poly(N-vinylcarbazole) Based Non-Volatile Memory Devices

Summary: The organic non-volatile memory devices (NVMs) based on poly(N-vinylcarbazole) (PVK) with the different structures and compositions were fabricated and evaluated. The resistance states in the devices were controlled by the external electric field and exhibited the distinctive properties; the device with a single PVK layer was a write-once read-many-times memory by the field induced filament as a conduction path and its memory properties depended on the PVK thickness, the PVK/Al/PVK structured device was operated by a space charge limited current model and was sensitive to preparing condition of the internal Al layer, and the device performances with the PVK based charge transfer complex depended on the composition of the CT materials and the surface condition of the bottom electrode.     

双掺杂和三掺杂铌酸锂晶体稳定全息存储的实验研究

对两种不同氧化 还原处理下的四种不同掺杂Cu∶Ce ,Mn∶Cu∶Ce ,Mn∶Fe和Mn∶Fe∶Mg的铌酸锂晶体进行了红光和紫光光色效应稳定全息存储的实验研究 ,实现了LiNbO3∶Cu∶Ce和LiNbO3∶Mn∶Cu∶Ce晶体中的稳定全息存储。实验结果表明只有高氧化的晶体才能实现稳定全息存储。在高信噪比前提下 ,LiNbO3∶Cu∶Ce晶体稳定衍射效率最高。     

MBE生长的垂直堆垛InAs量子点及HFET存储器件的应用

用MBE设备以Stranski-Krastanov生长方式外延生长了5个周期垂直堆垛的InAs量子点，在生长过程中通过对量子点形状，尺寸的控制来提高垂直堆垛InAs量子点质量和均匀性，用原子力显微镜（AFM）进行表面形貌的表征，并利用光致发光（PL）和深能级瞬态谱（DLTS）对InAs量子点进行观测。所用Al0.5Ga0.5As势垒外延层，对镶嵌在其中的InAs量子占粗很强的量子限制作用，并产生强量子限制效应，可以把InAs量子点的电子和空穴能级的热激发当作“深能级”的热激发来研究，这样可用DLTS方法进行测量，在垂直堆垛的InAs量子点的HFET器件中，由充电和放电过程的IDS－VGS曲线可以看到阈值电压有非常大的移动，这样便产生存储效应。     

Simulation study of new 3-terminal devices for high speed STT-RAM

To improve the performance of spin transfer torque random access memory(STT-RAM),especially writing speed,we propose three modified 3-terminal STT-RAM cells.A magnetic dynamic process in the new structures was investigated through micro-magnetic simulation.The best switching speed of the new structures is 120%faster than that of the rectangular 3-terminal device.The optimized 3-terminal device offers high speed while maintaining the high reliability of the 3-terminal structure.     

基于新型非易失存储器的混合内存架构的内存管理机制

随着互联网和云计算技术的迅猛发展,现有动态随机存储器（Dynamic Random Access Memory,DRAM）已无法满足一些实时系统对性能、能耗的需求.新型非易失存储器（Non-Volatile Memory,NVM）的出现为计算机存储体系的发展带来了新的契机.本文针对NVM和DRAM混合内存系统架构,提出一种高效的混合内存页面管理机制.该机制针对内存介质写特性的不同,将具有不同访问特征的数据页保存在合适的内存空间中,以减少系统的迁移操作次数,从而提升系统性能.同时该机制使用一种两路链表使得NVM介质的写操作分布更加均匀,以提升使用寿命.最后,本文在Linux内核中对所提机制进行仿真实验.并与现有内存管理机制进行对比,实验结果证明了所提方法的有效性.     

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.     

Molecular-scale charge trap medium for organic non-volatile memory transistors

In this work, we introduce a molecular-scale charge trap medium for an organic non-volatile memory transistor (ONVMTs). We use two different types of small molecules, 2,3,6,7,10,11-hexahydroxytriphenylene (HHTP) and 2,3,6,7,10,11-hexamethoxytriphenylene (HMTP), which have the same triphenylene cores with either hydroxyl or methoxy end groups. The thickness of the small molecule charge trap layer was sophisticatedly controlled using the thermal evaporation method. X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared (FTIR) analysis revealed that there were negligible differences in the chemical structures of both small molecules before and after thermal deposition process. The ONVMTs with a 1-nm-thick HHTP charge trap layer showed a large hysteresis window, approximately 20 V, under a double sweep of the gate bias between 40 V and −40 V. The HMTP-based structure showed a negligible memory window, which implied that the hydroxyl groups affected hysteresis. The number of trapped charges on the HHTP charge trap layer was measured to be 4.21 × 10¹² cm⁻². By varying the thickness of the molecular-scale charge trap medium, it was determined that the most efficient charge trapping thickness of HHTP charge trap layer was approximately 5 nm.     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即 MFIS(Metal/Ferroelectric /Insulator/Semiconductor)电容的方法,并对其进行了SEM、C- V特性测试及ZrO2介质层介电常数分析 .研究了C-V存储窗口(Memory Window)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7～10左右 ,在外加电压-5V～+5V时存储窗口可达2.52 V左右 .     

Dual-Crossbar Configurated Bi2O2Se Device for Multiple Optoelectronic Applications

Two-dimensional (2D) materials are widely used in numerous optoelectronic devices due to their ultra-thin dimensions and versatile surfaces. However, less attention is paid to distinguishing the light-matter interactions along the vertical and horizontal paths within the same 2D lattice, as well as comparatively investigating the optoelectronic behaviors between the sensitive top and bottom surfaces. Here, a dual-crossbar configured architecture is designed and constructed based on Bi₂O₂Se semiconductor, featuring highly compact three-in-one assembly, namely bottom surface horizontal (BSH), middle sandwich vertical (MSV) and top surface horizontal (TSH) devices. The MSV with nanoscale channel possesses efficient separation and transportation of the photogenerated electrons and holes, responding faster to the light stimulation and compared favorably to the BSH and TSH devices. The optoelectric behaviors of the BSH device can be regulated by the characteristics of the substrate due to closer contact. Nevertheless, the performance of the TSH device is more sensitive to the environment, such as dopant absorption and heat dispersion, thus enabling the non-volatile photoresponse and can be employed as an artificial optoelectronic synapse. This work highlights the importance of designing the device architecture based on the intrinsic structural advantages of 2D materials, paving the way toward integrated optoelectronics.