A new FIFO for transferring data between two unrelated clock domains

A new simple-to-design FIFO that allows data transfer between two clock domains of unrelated frequencies has been developed. The fully synchronous interfaces significantly ease the system-on-chip integration process. With a relatively low gate count, the proposed FIFO allows the producer and consumer to put/get data at their respective frequencies (1?datum/clock cycle) till it gets filled, then the rates converge to the lower of the two frequencies. The maximum initial latency is three cycles of the consumer's clock. Several manifestations of the FIFO have been developed for different design cases including producer/consumer data width mismatch. Operation of the FIFO has been verified using both gate-level simulations and SPICE simulations with a 0.13?µm, 1.2?V technology. An 8-cell FIFO showed proper operation at producer and consumer clock frequencies of 2 and 3.125?GHz, respectively, with a data transfer rate of more than 2?giga datum/s and an average power of 721?µW.     

一种动态分配输入队列的片上虫孔路由器结构

为了降低片上网络（NoC）由于虫孔缓冲结构排头（HoL）阻塞导致的性能损失,同时消除虚通道缓冲结构对可变长度报文表现出的缓冲区低利用率现象,本文采用虚拟通道技术提出一种动态分配输入队列（DAIQ）的片上虫孔路由器结构.该结构采用一种令牌表的方式支持虚拟队列深度与数量的动态分配,同时为了支持同一报文微片能够连续调度,本文还提出一种新颖的开关分配机制——SRRM,该机制在高负载下进一步改善了开关的延迟与吞吐率.仿真与综合的结果表明,相比传统虚通道流控的片上路由器结构,DAIQ路由器以50%的缓冲面积获得类似的性能,在0.13微米CMOS工艺下节约了30.18%的标准单元面积与384%的功耗.     

面向性能优化的可重构片上网络技术研究

片上网络已经成为众核时代最具潜力的片上互连解决方案.然而,现有片上网络灵活性不足,无法支持通信的动态行为.研究具有高度灵活性、适应性和可配置性的可重构片上网络,对于提高复杂应用的通信效率具有重要意义.介绍了可重构片上网络的研究背景和相关研究,提出了一个面向可重构片上网络的系统化研究框架,阐述了可重构片上网络的重要研究点,给出了相关研究结果及实验数据.     

Low-cost regional-based congestion-aware routing algorithm for 2D mesh NoC

Given the advantages of network-on-chips (NoCs), they are rapidly improving to replace other forms of System-on-Chip (SoC) designs. Although various factors improve the NoC's performance, many challenges should be addressed when designing an NoC, one of which is congestion and its impacts on performance and efficiency. Hence, numerous routing algorithms have been proposed that contemplate the congestion influences to deal with its complexities. Nevertheless, given the significant impacts of overheads on performance and efficiency, it is crucial to consider them when designing an enhanced NoC. The proposed routing algorithm employs regional traffic information within multiple clusters and has a decent view of the traffic condition when choosing the path to the destination. Each node generates one bit of traffic information and propagates it only when the node is congested, thus preventing the information overhead. Finally, the path diversity parameter is utilized to identify the best route from the source to the destination. The proposed algorithm's results show that the number of received packets, average latency, average throughput, maximum latency, and energy consumption while using different traffic patterns are improved by 10.9%, 35.3%, 15.8%, 43%, and 15.3%, respectively.     

针对路径故障与局部拥塞的NoC容错路由算法

片上网络作为一种新型片上互连架构,克服了片上系统在发展中遭遇的瓶颈问题。然而,片上网络中的路由器故障以及路由器之间的链路故障都会造成网络性能损失。对此,文章提出一种针对路径故障与局部拥塞的NoC容错路由算法。首先,设计了一种相隔节点间路径故障模型,该模型下的路由器以较小的开销为代价,动态感知两跳以内的路径故障状态。其次,提出了一种新颖的更能准确反映局部网络拥塞状态的拥塞模型来均衡网络流量。最后,当网络无故障时,算法保证走最优路径;有故障时,算法不仅可以实现容错还能保证网络具有良好的性能。实验表明,在无故障的情况下,本文方案相较于对比对象延迟降低了10％～20％,吞吐率提高了25％左右。在有故障的情况下,本文方案较对比对象的优势更加明显。     

一种基于BFT型拓扑结构片上网络低费用测试方法

随着集成电路制作工艺的进步,多核与众核系统是片上系统的发展趋势.传统的二维网格(2D-mesh)型拓扑结构通信效率低、功耗高和时延长等缺点变得越来越明显.本文首先分析对比了几种常用拓扑结构在多核与众核情况下的性能,进而采用布线复杂度较低、性能较好的蝴蝶型胖树(BFT)拓扑结构来解决片上系统的设计和测试问题.随后,本文针...     

Thermal-aware test scheduling using network-on-chip under multiple clock rates

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.     

基于FPGA的片上网络虚拟通道控制器的设计

虚拟通道控制器的设计是实现虚拟通道技术的关键.基于FPGA实现技术,利用VHDL硬件描述语言设计实现了一种适用于网格、半环网、环网三种拓扑结构的虚拟通道控制器.该虚拟通道控制器工作频率能够达到689MHz,FPGA资源占用率仅为1%,是一种高效的虚拟通道控制器设计方案.     

基于SvstemC的支持异源通信实体的NoC仿真架构

片上网络为具有多个处理单元的高速并行片上系统提供一种结构化的片上通信与互连的方法。当前丰富多样的通信实体的选择、建模和仿真，对于精确评估和优化片上网络的整体性能非常重要。本文提出了一种基于SystemC的片上网络仿真和评估构架，以结构化、自动化的方式，支持基于当前通信实体的NoC仿真和设计流程。     

基于蚁群混沌遗传算法的片上网络映射

蚁群算法可以在兼顾功耗和负载平衡的情况下进行任务映射,但是由于传统蚁群算法对初始化参数的设置比较敏感,所以使用遗传算法来调整蚁群算法参数,在蚁群算法陷入局部最优时引入混沌模型来修改蚁群参数,修改后的算法在能耗方面相较于传统算法改善了11％,在负载平衡方面改善了1％,两者联合优化改善了4％.