Towards Strong Duality in Integer Programming

We consider in this paper the Lagrangian dual method for solving general integer programming. New properties of Lagrangian duality are derived by a means of perturbation analysis. In particular, a necessary and sufficient condition for a primal optimal solution to be generated by the Lagrangian relaxation is obtained. The solution properties of Lagrangian relaxation problem are studied systematically. To overcome the difficulties caused by duality gap between the primal problem and the dual problem, we introduce an equivalent reformulation for the primal problem via applying a pth power to the constraints. We prove that this reformulation possesses an asymptotic strong duality property. Primal feasibility and primal optimality of the Lagrangian relaxation problems can be achieved in this reformulation when the parameter p is larger than a threshold value, thus ensuring the existence of an optimal primal-dual pair. We further show that duality gap for this partial pth power reformulation is a strictly decreasing function of p in the case of a single constraint. Dedicated to Professor Alex Rubinov on the occasion of his 65th birthday. Research supported by the Research Grants Council of Hong Kong under Grant CUHK 4214/01E, and the National Natural Science Foundation of China under Grants 79970107 and 10571116.     

单模光纤中模耦合微扰功率谱与偏振关系的研究

提出用测量光纤偏振耦合率来确定模耦合系数，从而得到耦合微扰功率谱与双折射关系。它给出了光纤拉制中微扰作用 的信息，是研制偏振光纤的一种有效方法。     

A 24-GHz Patch Array with a Power Amplifier/Low-Noise Amplifier MMIC

This paper presents an active patch array designed at 24 GHz. It can be used as a front-end component for a phased array. A series resonant array structure is chosen which is compact and easy excite. With 5 elements, the array proved a 12-dB antenna gain. A power amplifier and a low noise amplifier are designed on a single GaAs chip (PALNA). Bias switch is used in the PALNA, which greatly reduces the switch loss in a transceiver and increases the efficiency. 20-dB small signal gain is achieved in both power amplifier and low noise amplifier. The active patch array is built by the combination of the patch array and PALNA. The measured active gain of this antenna is 35-dB for the PA mode and 31-dB for the LNA mode. This active patch array can obtain an EIRP of 34 dBm with a total radiated power of 22dBm and a maximum PAE of 32%. To check the noise performance, we applied sources at both normal temperature and 77K (liquid nitrogen) and extracted the noise figure (3.5 dB) of the active antenna by the Y factor method. The results proved that the active antenna is working efficiently as both a transmitting and receiving antenna.     

Sums of Two Exact Powers

An asymptotic formula is obtained for the number of representations of an element of a finite field as a weighted sum of two prescribed powers of primitive elements. This generalises previous work on sums of primitive elements, including that relating to some conjectures of Golomb.     

溅射功率对多层膜质量的影响

用磁控溅射技术制备薄膜，用X射线衍射研究在基片和靶间距离固定的情况下不同的溅射功率对薄膜结构的影响。结果表明：过低的溅射功率下淀积的薄膜有畸变的X射线衍射特征峰，特征峰强度小，半峰全宽大。而比较高溅射功率得到的薄膜有比较尖锐的X射线衍射特征峰，强度高和半峰全宽非常窄。研究表明，X射线衍射特征峰强度小和半峰全宽大的薄膜结构疏松，而强度高和半峰全宽非常窄的薄膜结构致密。     

群时延精确设计的全差分四阶Bessel滤波器

采用MOS管有源电阻,提出了一种全差分R-MOSFET-C四阶Bessel有源低通滤波器,.通过调节工作于亚阈值区的CMOS管的沟道导纳补偿电阻值的大小,能抵消集成电路制造工艺中电阻值的一致偏差,实现Bessel有源滤波器群时延的精确设计.根据无源滤波器的状态方程完成有源滤波器的综合,应用3.3V,0.5μm CMOS工艺完成了群时延大小为0.75μs的四阶Bessel低通滤波器的管极计算机仿真,仿真结果表明所提电路正确有效,适于全集成.     

受激喇曼散射在掺铒光纤放大器中的影响

本文在分析了均匀掺杂分布式光纤放大器（d－EDFA）的基础上，提出了沿传输方向掺杂浓度单调下降（单变），和降升结合（两变）的两种渐变型分布式光纤放大器，并用传输方程研究了透明传输和最佳掺杂浓度下，受激喇曼散射对均匀、单变和两变型三种d－EDFA的各种特性的影响．     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

PIC单片机在激光电源中的应用研究

论述了单片机控制激光电源的原理，提出了产生PWM控制的基本思想及整个控制系统的硬件组成和软件设计方法。     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.