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11.
Information‐Centric Networking (ICN) has been accepted to overcome some weaknesses of the current Internet architecture, showing that “what is being exchanged” is more important than “who are exchanging information.” Given the inadequate considerations on Quality of Service (QoS) and energy saving in ICN routing, we propose in this paper a routing algorithm to enhance the two aspects. At first, on one hand, Cauchy distribution is used as a fuzzy model to evaluate users' QoS requirements, such as bandwidth, delay, and error rate; on the other hand, we formulate energy saving problem to evaluate the green quality of routing algorithm. Then, we design a link selection approach by considering QoS and energy saving, which belongs to a multi‐objective decision problem resolved by intelligent drops algorithm. Finally, we implement the proposed algorithm and compare it with the famous adaptive forwarding mechanism in terms of some significant metrics, and the experimental results reveal that the proposed algorithm is more efficient. 相似文献
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基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。 相似文献
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Shi-Tao Han Hong-Ying Duan Lan-Yun Chen Dr. Tian-Guang Zhan Dr. Li-Juan Liu Li-Chun Kong Prof. Kang-Da Zhang 《化学:亚洲杂志》2021,16(23):3886-3889
A photo-switchable hetero-complementary quadruple H-bonding array, which consists of an azobenzene-derived ureidopyrimidinone (UPy) module ( Azo-UPy ) and a nonphotoactive diamidonaphthyridine (DAN) derivative ( Napy-1 ), is constructed based on a reversible photo-locking approach. Upon UV (390 nm)/Vis (460 nm) light irradiations, photo-switchable quadruple H-bonded dimerization between Azo-UPy and Napy-1 can be achieved with exhibiting 4.8×104-fold differences in binding strength (ON/OFF ratios). Furthermore, smart polymeric gels with unique photo-controlled macroscopic self-assembly behavior can be fabricated by introducing such quadruple H-bonding array as photo-regulable noncovalent interfacial connections. 相似文献
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1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm2 is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm2 array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall Vmin of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances. 相似文献
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Namyong Kim 《ETRI Journal》2006,28(2):155-161
In this paper, we introduce an escalator (ESC) algorithm based on the least squares (LS) criterion. The proposed algorithm is relatively insensitive to the eigenvalue spread ratio (ESR) of an input signal and has a faster convergence speed than the conventional ESC algorithms. This algorithm exploits the fast adaptation ability of least squares methods and the orthogonalization property of the ESC structure. From the simulation results, the proposed algorithm shows superior convergence performance. 相似文献
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USB数据传输中CRC校验码的并行算法实现 总被引:8,自引:2,他引:6
文章介绍了用于USB总线数据传输的CRC校验的原理和算法,并且采用并行电路实现USB2.0中的CRC产生和CRC校验,与传统的串行电路实现相比,并行电路实现方法虽然在芯片面积上大于串行电路实现,但由于降低了时钟频率,电路更容易综合实现,并且大大降低了功耗,有利于低功耗电路设计。 相似文献
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