基于BP神经网络的LED可靠性模型研究

根据LED可靠性与相关参数的映射关系,建立拓扑结构为6-12-1的BP神经网络。以实测白光LED芯片的理想因子、结温、色温漂移等参数为输入量,以寿命为输出量,计算模型精度。研究结果表明,该模型有良好的外推能力及鲁棒性,可在短时间内成功预测LED寿命,神经网络训练结果相关系数为99.8%,检验组误差小于3%。     

冗余技术提高PLC控制系统可靠性的研究

针对工业现场对PLC控制系统可靠性提出更高的要求,提出利用冗余技术提高其可靠性。分析了硬件冗余和软件冗余在PLC控制系统中的应用,详细阐述了PLC控制器、输入输出口、通讯网络和电源各自的冗余方法,并着重以西门子300/400系列PLC为例进行了软硬件冗余的架构和原理分析。最后对冗余控制系统的可靠性进行分析,结果表明,使用冗余技术可使PLC控制系统的可靠性得到明显提高。     

一个可靠机器,一个不可靠机器和一个缓冲库构成的系统的定性分析

本文用纯分析的方法给出了一个可靠机器 ,一个不可靠机器和一个缓冲库构成的系统解的存在唯一性证明     

APPROXIMATING ANALYSIS OF A KIND OF REPAIRABLE STANDBY SYSTEMS

ＬＩＷＥＩ（李伟）；ＣＡＯＪＩＮＨＵＡ（曹晋华）（ＩｎｓｔｉｔｕｔｅｏｆＡｐｐｌｉｅｄＭａｔｈｅｍａｔｉｃｓ，ｔｈｅＣｈｉｎｅｓｅＡｃａｄｅｍｙｏｆＳｃｉｅｎｃｅｓ，Ｂｅｉｊｉｎｇ１０００８０，ＣｈｉｎａａｎｄＡｓｉａ－ＰａｃｉｆｉｃＯｐｅｒａｔｉｏ...     

Lifetime distribution and estimation problems of consecutive-k-out-of-n:F systems

Explicit formula is given for the lifetime distribution of a consecutive-k-out-of-n:F system. It is given as a linear combination of distributions of order statistics of the lifetimes of n components. We assume that the lifetimes are independent and identically distributed. The results should make it possible to treat the parametric estimation problems based on the observations of the lifetimes of the system. In fact, we take up, as some examples, the cases where the lifetimes of the components follow the exponential, the Weibull, and the Pareto distributions, and obtain feasible estimators by moment method. In particular, it is shown that the moment estimator is quite good for the exponential case in the sense that the asymptotic efficiency is close to one.This research was partially supported by the ISM Cooperative Research Program (94-ISM-CRP-5).     

我国工业污染分布状况研究

环境污染越来越受到我国的重视,而工业污染是造成环境污染的重要原因.为了对我国的环境污染分布状况进行深入了解,从总量出发,利用聚类分析和因子分析法分析了我国工业污染的分布情况,并探讨了各类地区工业污染差异的原因,为我国进行侧重点治理环境污染提出可行性建议.     

Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis

Time-dependent dielectric breakdown (TDDB) has become an important cause of failure for inter-metal dielectrics (IMD) in integrated circuits as feature sizes continue to shrink and novel materials are introduced. Although many studies have been conducted to understand the underlying physics of this issue, not enough work has been focused on evaluating TDDB lifetime of practical chip designs in the physical design stage. This paper proposes a full-chip TDDB failure analysis methodology to evaluate lifetime and identify TDDB hotspots in VLSI layouts, which are essentially interconnect wires that have high failure risk due to TDDB. The proposed method features three new techniques compared to existing methods. First, we have developed a partitioning-based scheme to deal with scaling of full-chip analysis by partitioning the full chip layout into small tiles. Second, for each tile, the new method calculates a newly-introduced TDDB failure metric called TDDB Damage for vulnerable wires. Such a wire-oriented TDDB analysis is the first of its kind and is very amenable for physical design as the wires can be easily adjusted or re-routed for TDDB-aware optimization. Third, the new method considers the impact of the non-uniform electric field calculated using the finite element method (FEM), which significantly improves the accuracy of TDDB risk evaluation. Experimental results show that the proposed new TDDB analysis method is more accurate than a recently proposed full-chip TDDB analysis method in which electrical field is treated as a constant value. Additionally, the proposed method can analyze a practical VLSI layout in a few hours.     

Precise Extraction of Charge Carrier Mobility for Organic Transistors

Unreliable mobility values, and particularly greatly overestimated values and severely distorted temperature dependences, have recently hampered the development of the organic transistor field. Given that organic field‐effect transistors (OFETs) have been routinely used to evaluate mobility, precise parameter extraction using the electrical properties of OFETs is thus of primary importance. This review examines the origins of the various mobilities that must be determined for OFET applications, the relevant extraction methods, and the data selection limitations, which help in avoiding conceptual errors during mobility extraction. For increased precision, the review also discusses device fabrication considerations, calibration of both the specific gate‐dielectric capacitance and the threshold voltage, the contact effects, and the bias and temperature dependences, which must actually be handled with great care but have mostly been overlooked to date. This review serves as a systematic overview of the OFET mobility extraction process to ensure high precision and will also aid in improving future research.     

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

The continuous miniaturization of field effect transistors (FETs) dictated by Moore's law has enabled continuous enhancement of their performance during the last four decades, allowing the fabrication of more powerful electronic products (e.g., computers and phones). However, as the size of FETs currently approaches interatomic distances, a general performance stagnation is expected, and new strategies to continue the performance enhancement trend are being thoroughly investigated. Among them, the use of 2D semiconducting materials as channels in FETs has raised a lot of interest in both academia and industry. However, after 15 years of intense research on 2D materials, there remain important limitations preventing their integration in solid‐state microelectronic devices. In this work, the main methods developed to fabricate FETs with 2D semiconducting channels are presented, and their scalability and compatibility with the requirements imposed by the semiconductor industry are discussed. The key factors that determine the performance of FETs with 2D semiconducting channels are carefully analyzed, and some recommendations to engineer them are proposed. This report presents a pathway for the integration of 2D semiconducting materials in FETs, and therefore, it may become a useful guide for materials scientists and engineers working in this field.     

Conductive adhesive with transient liquid‐phase sintering technology for high‐power device applications

A highly reliable conductive adhesive obtained by transient liquid‐phase sintering (TLPS) technologies is studied for use in high‐power device packaging. TLPS involves the low‐temperature reaction of a low‐melting metal or alloy with a high‐melting metal or alloy to form a reacted metal matrix. For a TLPS material (consisting of Ag‐coated Cu, a Sn96.5‐Ag3.0‐Cu0.5 solder, and a volatile fluxing resin) used herein, the melting temperature of the metal matrix exceeds the bonding temperature. After bonding of the TLPS material, a unique melting peak of TLPS is observed at 356 °C, consistent with the transient behavior of Ag₃Sn + Cu₆Sn₅ → liquid + Cu₃Sn reported by the National Institute of Standards and Technology. The TLPS material shows superior thermal conductivity as compared with other commercially available Ag pastes under the same specimen preparation conditions. In conclusion, the TLPS material can be a promising candidate for a highly reliable conductive adhesive in power device packaging because remelting of the SAC305 solder, which is widely used in conventional power modules, is not observed.