A Bist Scheme for Non-Volatile Memories

A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.     

Soft errors in floating gate memory cells: A review

Soft errors due to neutrons and alpha particles are among the main threats for the reliability of digital circuits operating at terrestrial level. These kinds of errors are typically associated with SRAMs and latches or DRAMs, and less frequently with non-volatile memories. In this paper we review the studies on the response of NAND and NOR Flash memories to ionizing particles, focusing on both single-level and multi-level cell architectures, manufactured in technologies down to a feature size of 25 nm. We discuss experimental error rates obtained with accelerated tests and identify the relative importance of neutron and alpha contributions. Technology scaling trends are finally discussed and modelled.     

Comprehensive numerical simulation of threshold-voltage transients in nitride memories

A new non-local algorithm for accurately calculating the band-to-band tunneling current suitable for TCAD semiconductor simulators is proposed in this paper. The proposed algorithm captures the essential physics of multi-dimensional tunneling in a 2D structure, and is designed to be robust and to achieve independence on the mesh grid. The new algorithm enables accurate modeling of T-FET and investigation of its device physics.     

Kosko型双向联想记忆与Hopfield神经网络的关系

深入理解K0sko型双向联想记忆(BAM)网络是学习使用其它双向联想记忆的基础.如果我们按照传统的方法介绍BAM网络,学生很容易产生两个疑问:能量函数为什么是定义的?BAM网络与Hopfield网络的内在联系是什么?本文在说明Kosko型BAM网络就是一种特殊的Hopfield网络后,从Hopfield网络的能量函数出...     

Multibit Programmable Optoelectronic Nanowire Memory with Sub‐femtojoule Optical Writing Energy

Persistent challenges in the nanofabrication of optoelectronic memory elements with ready size‐scalability, multibit data storage, and ultralow optical writing energy have limited progress toward the construction of optical data storage/buffering elements in high‐density photonic‐electronic circuits. Here, a multibit programmable optoelectronic nanowire (NW) memory is described that operates with an ultralow optical writing energy [ca. 180 aJ bit^?1 (ca. 330 photons bit^?1)] and a low standby power consumption (<1 pW) at room temperature. In this system, photoionized charged defects behave as surface trapped charges to achieve the electrical memory effect. As a result of the high surface electric field, the rate of dissociation of the photoexcited charge is amplified, thereby decreasing the optical writing energy. Moreover, the extremely high dynamic photoconductive gain (ca. 10¹⁰) makes it possible to write multibit optical data bit‐by‐bit into the NW. These findings should open new opportunities in next‐generation multifunctional nanochips for optical data storage/buffering, optical data processing, and optical sensing purposes.     

Reversible Ferromagnetic Phase Transition in Electrode‐Gated Manganites

The electronic phase transition has been considered as a dominant factor in the phenomena of colossal magnetoresistance, metal‐insulator transition, and exchange bias in correlated electron systems. However, the effective manipulation of the electronic phase transition has remained a challenging issue. Here, the reversible control of ferromagnetic phase transition in manganite films through ionic liquid gating is reported. Under different gate voltages, the formation and annihilation of an insulating and magnetically hard phase in the magnetically soft matrix, which randomly nucleates and grows across the film instead of initiating at the surface and spreading to the bottom, is directly observed. This discovery provides a conceptually novel vision for the electric‐field tuning of phase transition in correlated oxides. In addition to its fundamental significance, the realization of a reversible metal‐insulator transition in colossal magnetoresistance materials will also further the development of four‐state memories, which can be manipulated by a combination of electrode gating and the application of a magnetic field.     

A System Design Methodology for Analog Feed Forward Artificial Neural Networks

Today Feed Forward Neural Networks (FFNs) use paradigms tied to mathematical frameworks more than to actual electronic devices. This fact makes analog neural integrated circuits heavy to design. Here we propose an alternative model that can use the native computational properties of the basic electronic circuits. A practical framework is described to train analog FFNs in compliance with the model. This is especially useful whenever the weight storage elements cannot be re-programmed on the fly at a high rate. To show how the capability of such framework can be applied to neural systems with non conventional architectures two cases are presented. The first one is a neural signal processor named NESP which has sigmoidal neurons and the other is an innovative architecture named N-LESS.     

A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques

This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuitry embedded in a BIST wrapper, and an ATE test program to schedule the data extraction flow and to analyze the gathered information. Testing is performed exploiting a standard IEEE 1149.1 TAP, which allows the access to multiple memory cores with a P1500 compliant solution. The approach aims at implementing a low-cost solution to diagnose embedded RAMs with the goal to minimize the ATE costs and the time required to extract the diagnostic information. In our approach, the ATE drives the diagnostic scheme and performs the classification of faults, allowing the adoption of low-cost equipments. The proposed solution allows a scalable extraction of test data, whose amount is proportional to the available testing time. In order to accelerate fault classification, image processing techniques have been applied. The Hough transform has been adopted to analyze the bitmap representing the faulty cells. Experimental results show the advantages of the proposed approach in terms of time required to complete the diagnostic process.     

Scaling potential of pin-type 3-D SBT ferroelectric capacitors integrated in 0.18 μm CMOS technology

In this work, the difficult scaling of FeRAM is circumvented by fabricating 3-dimensional ferroelectric capacitors stacked on W plugs and successfully integrated in 0.18 μm technology using MOCVD SBT. The effective remnant polarization was increased by 70% due to the sidewall contribution. Also, high reliability of 3-D capacitors was assessed. The samples showed no fatigue degradation after 10¹³ ±5 V cycles. From extrapolation of both imprint and retention results, a wide sensing window is kept after 10 years in most severe temperature condition, that is at 150 °C. Critical integration issues are discussed for further scaling in 0.13 μm technology and below.     

Minimal March Tests for Detection of Dynamic Faults in Random Access Memories

The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of Random Access Memories (RAM) with significant impact on defect-per-million (DPM) levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults, respectively, were proposed recently [Benso et al., Proc., ITC 2005] improving the length of the corresponding tests proposed earlier [Hamdioui et al., Proc. of IEEE VLSI Test Symposium, pp. 395–400, 2002]. Also, a March test of length 100N was proposed [Benso et al., Proc. ETS 2005, Tallinn, pp. 122–127, 2005] for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, March test algorithms of minimum length are proposed for two-operation single-cell and two-cell dynamic faults. In particular, the previously known March test algorithm of length 100N for detection of two-operation two-cell dynamic faults is improved by 30N.