Investigation of light programmable non‐volatile memory in an organic phototransistor

Excellent non‐volatile memory characteristics have been demonstrated under the optoelectric conditions for organic phototransistors (OPTs). The high photosensitivity shown as reversible shifts in light‐induced V_TH exhibits a large memory window for programming caused by the excited immobile carriers (electron) trapped as a function of the electrical bias and the light intensity. The long life span of stored electrons also reveals promising behavior with respect to data retention as well as the electrical reliability to serve as a data storage medium with the non‐volatile memory characteristic in OPTs. The V_TH recovery accelerated by the reversible bias stress for the stored charges under irradiation shows that the erasing behavior is clearly brought by the discharge process of long‐lived electrons occupied in deep states. Plausible mechanisms in the energy band are discussed for the programming and erasing process, which provides a fundamental understanding of the intrinsic charge storage behavior in OPTs. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Dynamic moderation of an electric field using a SiO2 switching layer in TaOx ‐based ReRAM

ReRAMs using oxygen vacancy drift in their resistive switching are promising candidates as next generation memory devices. One remaining issue is degradation of the on/off ratio down to 10² or less with an increased number of switching cycles. Such degradation is caused by a local hard breakdown in a set process due to a very high electric field formed just before the completion of a conductive filament formation. We found that introducing an ultra‐thin SiO₂ layer prevents the hard breakdown by dynamical moderation of the electric field formed in the TaO_x matrix, resulting in repeated switching while retaining a higher on/off ratio of about 10⁵. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Analysis of nitride storage non-volatile memories with HfSiOx blocking dielectric and TiN metal gate for low power embedded applications

Nitride storage non-volatile memories with hafnium silicate (HfSiO_x) blocking dielectric and titanium nitride (TiN) metal gate aimed at low power embedded applications beyond the 45 nm node, have been fabricated and investigated. In addition to presenting the typical figures of merit of flash memories, the scalability of the devices has been assessed. We have also investigated the physical origin of the observed memory features.     

A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture

In this work, a new technologic strategy that allows implementing large crossbars formed with memFETs, a new device concept, is introduced. This memFET is an electrically reconfigurable field effect and resistive switching device that can be used to implement logic functions and memory blocks into a crossbar structure, allowing the dynamic logic configuration of the crossbar and simplifying both the design and the implementation of computing hardware. Moreover, taking the advantage of reconfiguration capability of such a technology and architecture we introduce a novel technique to design evolvable hardware where not only the logic functions are changeable (as is the case of the Field Programmable Gate Array, FPGA) but also the physical position of the components on the surface of the integrated circuit. This technology and principle leads towards a new computing paradigm based on what we name Shape Shifting Digital Hardware (SSDH).     

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation

Exceptionally leaky transistors are increasingly more frequent in nanometer-scale technologies due to lower threshold voltage and its increased variation. SRAM cells containing such transistors suffer from accelerated aging due to electromigration intensified by higher currents continuously flowing through thin metals such as vias and contacts. Such cells do not violate target delay since leaky transistors are faster than ideal ones, and hence they are not faulty to be worth replacing with redundant rows and columns, which may also themselves contain exceptionally leaky transistors. Moreover, their number is growing so fast that makes redundancy ineffective. We show that in SRAM cells leakage current depends on the value stored in the cell and propose a software-based runtime technique that suppresses such abnormal leakages in the standby mode by storing safe values in the corresponding cache lines. Consequently, the lifetime of such caches is restored when used in long-standby applications. Moreover, energy dissipation in the standby mode is reduced by this technique if the standby duration is more than a few seconds. Analysis proves the performance penalty is, in the worst case, linearly dependent to the number of so-cured cache lines.     

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories

This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of the code correction ability and efficiency. Furthermore, we will show that a minimal increase in the redundancy with respect to the standard case allows a further considerable reduction of the impact on memory access time and area overhed due to the error correction circuitry.     

一类模糊双向联想记忆网络极限环的最大长度

讨论了一类模糊双向联想记忆网络极限环的最大长度.首先,A是强连通布尔矩阵时,极限环的最大长度是A的周期指数per(A);其次,A具有形式(☆)时,若gcd(per(A1),per(A2))=1,则极限环的最大长度为max(per(A1),per(A2));若gcd(per(A1),per(A2))≥2,则其最大长度为lcm(per(A1),per(A2));最后对其进行推广.     

A Bist Scheme for Non-Volatile Memories

A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.     

Soft errors in floating gate memory cells: A review

Soft errors due to neutrons and alpha particles are among the main threats for the reliability of digital circuits operating at terrestrial level. These kinds of errors are typically associated with SRAMs and latches or DRAMs, and less frequently with non-volatile memories. In this paper we review the studies on the response of NAND and NOR Flash memories to ionizing particles, focusing on both single-level and multi-level cell architectures, manufactured in technologies down to a feature size of 25 nm. We discuss experimental error rates obtained with accelerated tests and identify the relative importance of neutron and alpha contributions. Technology scaling trends are finally discussed and modelled.     

Comprehensive numerical simulation of threshold-voltage transients in nitride memories

A new non-local algorithm for accurately calculating the band-to-band tunneling current suitable for TCAD semiconductor simulators is proposed in this paper. The proposed algorithm captures the essential physics of multi-dimensional tunneling in a 2D structure, and is designed to be robust and to achieve independence on the mesh grid. The new algorithm enables accurate modeling of T-FET and investigation of its device physics.