Towards engineering in memristors for emerging memory and neuromorphic computing:A review

Resistive random-access memory(RRAM),also known as memristors,having a very simple device structure with two terminals,fulfill almost all of the fundamental requirements of volatile memory,nonvolatile memory,and neuromorphic characteristics.Its memory and neuromorphic behaviors are currently being explored in relation to a range of materials,such as biological materials,perovskites,2D materials,and transition metal oxides.In this review,we discuss the different electrical behaviors exhibited by RRAM devices based on these materials by briefly explaining their corresponding switching mechanisms.We then discuss emergent memory technologies using memristors,together with its potential neuromorphic applications,by elucidating the different material engineering techniques used during device fabrication to improve the memory and neuromorphic performance of devices,in areas such as ION/IOFF ratio,endurance,spike time-dependent plasticity(STDP),and paired-pulse facilitation(PPF),among others.The emulation of essential biological synaptic functions realized in various switching materials,including inorganic metal oxides and new organic materials,as well as diverse device structures such as single-layer and multilayer hetero-structured devices,and crossbar arrays,is analyzed in detail.Finally,we discuss current challenges and future prospects for the development of inorganic and new materials-based memristors.     

Status and Trends in Advanced SOI Devices and Materials

A review of recently explored effects in advanced SOI devices and materials is given. The effects of key device parameters on the electrical and thermal floating body effects are shown for various device architectures.Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. New hot carrier phenomena are discussed. The effects of gate misalignment or underlap,as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.     

QUALITATIVE ANALYSIS OF BIDIRECTIONAL ASSOCIATIVE MEMORY NEURAL NETWORKS

In this paper, the global exponential stability of an equilibrium position for general bidirectional associative memory neural networks are studied. The sufficient conditions of existence and uniqueness of the equilibrium position are given. The method of energy function is examined. Two examples are given to illustrate the theory.     

Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable resistive divider generates the staircase-shaped waveform needed for adequate ML programming accuracy as well as the read/verify voltage required for read and verify operations. A high-swing controlled-discharge circuit minimizes the settling time when switching from program to verify phases and vice versa. The same generator is used to provide the voltage required in read and in program mode, thus saving silicon area and minimizing current consumption. Experimental results of the proposed circuit integrated in a 4-level-cell 64-Mb NOR-type Flash memory are presented.     

Dynamic Programming and Diagnostic Classification

In this paper, the sequential determination of the Moore-Penrose generalized inverse matrix by dynamic programming is applied to the diagnostic classification of electromyography signals. The obtained results are comparable to those in the literature. Moreover, this recursive scheme has the advantage of allowing the inclusion of new diagnostic results in the learning process, as more and more patients are included in the training of the associative memory.     

On-chip testing of random access memories

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.Part of this work was completed when the author was a Visting Professor at the University of Roorkee, India.     

Resistive Random Access Memory Cells with a Bilayer TiO2/SiOX Insulating Stack for Simultaneous Filamentary and Distributed Resistive Switching

In order to fulfill the information storage needs of modern societies, the performance of electronic nonvolatile memories (NVMs) should be continuously improved. In the past few years, resistive random access memories (RRAM) have raised as one of the most promising technologies for future information storage due to their excellent performance and easy fabrication. In this work, a novel strategy is presented to further extend the performance of RRAMs. By using only cheap and industry friendly materials (Ti, TiO₂, SiO_X, and n⁺⁺Si), memory cells are developed that show both filamentary and distributed resistive switching simultaneously (i.e., in the same I–V curve). The devices exhibit unprecedented hysteretic I–V characteristics, high current on/off ratios up to ≈5 orders of magnitude, ultra low currents in high resistive state and low resistive state (100 pA and 125 nA at –0.1 V, respectively), sharp switching transitions, good cycle‐to‐cycle endurance (>1000 cycles), and low device‐to‐device variability. We are not aware of any other resistive switching memory exhibiting such characteristics, which may open the door for the development of advanced NVMs combining the advantages of filamentary and distributed resistive switching mechanisms.     

High‐Sensitivity Floating‐Gate Phototransistors Based on WS2 and MoS2

In recent years, 2D layered materials have been considered as promising photon absorption channel media for next‐generation phototransistors due to their atomic thickness, easily tailored single‐crystal van der Waals heterostructures, ultrafast optoelectronic characteristics, and broadband photon absorption. However, the photosensitivity obtained from such devices, even under a large bias voltage, is still unsatisfactory until now. In this paper, high‐sensitivity phototransistors based on WS₂ and MoS₂ are proposed, designed, and fabricated with gold nanoparticles (AuNPs) embedded in the gate dielectric. These AuNPs, located between the tunneling and blocking dielectric, are found to enable efficient electron trapping in order to strongly suppress dark current. Ultralow dark current (10^?11 A), high photoresponsivity (1090 A W^?1), and high detectivity (3.5 × 10¹¹ Jones) are obtained for the WS₂ devices under a low source/drain and a zero gate voltage at a wavelength of 520 nm. These results demonstrate that the floating‐gate memory structure is an effective configuration to achieve high‐performance 2D electronic/optoelectronic devices.     

双电层电容器发展现状及前景

分别介绍了目前生产双电层电容器有代表性的日本 Tokin公司、NEC公司、松下公司、EL NA公司和俄罗斯以及我国大庆华隆公司的典型产品的性能特点。论述了高等效串联电阻、中等效串联电阻及大功率双电层电容器的应用前景。双电层电容器作为一种能源供应新器件 ,在优化系统性能方面将起着越来越重要的作用