连续激光诱导Zn/InP掺杂过程中温度分布的解析计算

在实验的基础上，分析表面蒸发Zn的InP样品在连续激光诱导下掺杂Zn过程.在一维热传导问题的第三类边界条件下，给出激光辐照有限厚双层材料Zn/InP温度分布的一种直观简洁的解析形式. 关键词： 激光诱导掺杂 Zn/InP 温度分布     

微型生化分析仪样品室温度控制系统研究

结合微型生化分析仪样品室的要求,设计了一种基于单片机的微型生化分析仪样品室温度控制系统.它以AT89S51为核心,采用单总线高精度数字温度传感器DS18B20对样品室温度采样,同时利用汇编语言编写温度设定与控制程序,采用半导体制冷的方式,实现了温度在25℃、30℃、32℃和37℃四个温度值的稳定,控制精度达±0.5℃.     

From Long Infrared to Very Long Infrared Wavelength Focal Plane Arrays Made with HgCdTe n + n ?/ p Ion Implantation Technology

This paper aims at studying the feasibility of very long infrared wavelength (VLWIR) (12–18 μm) focal plane arrays using n-on-p planar ion-implanted technology. To explore and analyze the feasibility of such VLWIR detectors, a set of four Cd _x Hg_1−x Te LPE layers with an 18 μ cutoff at 50 K has been processed at Defir (LETI/LIR–Sofradir joint laboratory), using both our “standard” n-on-p process and our improved low dark current process. Several 320 × 256 arrays, 30-μm pitch, have been hybridized on standard Sofradir readout circuits and tested. Small dimension test arrays characterization is also presented. Measured photonic currents with a 20°C black body suggest an internal quantum efficiency above 50%. Typical I(V) curves and thermal evolution of the saturation current are discussed, showing that standard photodiodes remain diffusion limited at low biases for temperatures down to 30 K. Moreover, the dark current gain brought by the improved process is clearly visible for temperatures higher than 40 K. Noise measurements are also discussed showing that a very large majority of detectors appeared background limited under usual illumination and biases. In our opinion, such results demonstrate the feasibility of high-performance complex focal plane arrays in the VLWIR range at medium term.     

Synthesis and refractive‐index control of fluoropolymers by the polyaddition of bis(epoxide)s and triazine di(aryl ether)s

The polyaddition of fluorine‐containing bis(epoxide)s and fluorine‐containing triazine di(aryl ether)s were examined to give the corresponding fluorine‐containing poly(cyanurate)s. It was observed that the synthesized fluoropolymers had good thermal stabilities and good film‐forming properties. The glass transition temperatures (T_g's) and refractive‐indices (n_D's) of synthesized polymers were determined by differential scanning calorimetry and ellipsometry, respectively, and it was found that the values of T_g's and n_D's were supported by their fluorine containing ratios and skeletons. © 2007 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 45: 4421–4429, 2007     

Evidences of phase separation in moisture‐cured poly(urethane urea)s by means of temperature modulated differential scanning calorimetry

The degree of phase separation in several moisture‐cured poly(urethane urea)s (PUUs) was studied by FTIR spectroscopy, wide angle X‐ray diffraction (WAXD), and temperature‐modulated differential scanning calorimetry (TMDSC). This latter technique was shown to be particularly useful in analysing the degree of phase separation in PUU polymers. Both phase mixing and phase segregation coexisted in the PUUs and the degree of phase separation increased as the urea hard segment (HS) content in the PUU increased. The maximum solubility of urea HSs into the polyol soft segments (SSs) was achieved for 50 wt % urea HS content in diol‐based PUUs, whereas for triol‐based PUUs the highest solubility between HS and SS was reached for lower urea HS amount. Finally, the higher the urea HS content the higher the extent of phase separation in the PUU. © 2007 Wiley Periodicals, Inc. J Polym Sci Part B: Polym Phys 45: 3034–3045, 2007     

具有控制系数的高阶线性微分方程复振荡的一个结果

该文考虑具有控制系数 A\-0 和系数仅有有限个极点的高阶线性齐次微分方程（1.1）。得到了一个复振荡结果，该结果是J. K. Langley［11］等作者在整系数下相应结果的推广。     

碳纳米管阵列、捆束的三步升温工艺制备及其形貌与结构

使用结构简单的单温炉设备，通过三步升温热解二茂铁、三聚氰氨混合物方法，在二氧化硅、多晶陶瓷基底上分别合成了碳纳米管阵列、碳纳米管捆束.使用扫描电子显微镜、透射电子显微镜、电子能量损失谱和x射线光电子能谱对合成样品进行了结构和成分分析.结果显示：两种基底上合成的纳米管均为多壁纯碳管；生长于光滑二氧化硅表面的碳纳米管具有高度取向性和一致的外径，长度为10—40μm.碳纳米管采取催化剂顶端生长模式并展示出类杯状形貌；生长于粗糙多晶陶瓷表面的碳纳米管捆束随机取向，碳纳米管直径为15—80nm，长度在几百微米，展示 关键词： 碳纳米管 热解法 三步升温工艺     

32位MIPS微处理器中乘法器的设计和实现

在Booth算法的基础上,结合MIPS 4KC微处理器中的流水线结构和乘法器的工作过程,提出了一种改进的Booth乘法器的设计方法,并采用全制定方法实现,用这种方法实现的乘法器单元具有面积小、单元电路可重复性好、版图设计工作量小、功耗低等特点.     

SoC低功耗设计中的DVS技术

随着系统芯片(SoC)集成更多的功能并采用更先进的工艺,它所面临的高性能与低功耗的矛盾越来越突出.动态电压调整(DVS)技术可以在不影响处理器性能的前提下,通过性能预测软件根据处理器的繁忙程度调整处理器的工作电压和工作频率,达到降低芯片功耗的目的.文中讨论了DVS技术降低功耗的可能性,介绍了如何利用两种不同的DVS技术让处理器根据当前的工作负荷运行在不同的性能水平上,以节省不必要的功耗.     

一种低功耗Cache设计技术的研究

低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中，提出一种利用读／写缓冲器作为零级cache，减少对数据、指令cache的读／写次数，由于缓冲器读取功耗远远小于片上cache，从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证，该技术可减少对指令cache或者数据cache20％～40％的读取次数，以较小芯片面积的增加换取了较大的功耗降低。