基于FPGA的数字解扩解调模块设计及实现

提出了一种适用于直扩通信系统的解调解扩模块.分析了该电路的基本原理及其实现技术,详细讨论了各电路模块的设计实现方法,并采用自顶向下和模块化的设计思想,利用Verilog语言,通过仿真和综合,最后在FPGA上硬件实现.给出了电路实现后的仿真结果及RTL图,结果表明该环路性能优良,能够达到项目的设计指标要求,对工程设计有一定的参考价值.     

电调谐LC滤波器的研究与设计

介绍几种典型LC电调滤波器的设计原理和方法.研究设计一个VHF频段的电调滤波器,并使用Agilent公司的微波电路CAD软件ADS进行仿真.对制成品的实际测试和调试表明,此滤波器达到了预期的技术指标,性能良好.其工作频段为100～250 MHz,3 dB带宽为7～10 MHz左右,通带插损小于1 dB,带外抑制大于30 dB,幅频一致性好.对LC电调滤波器的设计具有指导作用.     

二维环的快速选取与自动识别

二维图形处理中,二维闭合环的选取和自动判别是问题关键.通过对二维图形进行网格划分,减少了环选取过程中浮点运算量,提高了环选取的速度.还给出了一种二维闭合环的自动识别算法,通过该算法,不需人工干预,可以自动生成环关系的树状拓扑结构,从而正确判别各环之间的拓扑关系.     

Novel Quasi‐Elliptic Function Bandpass Filter Using Hexagonal Resonators with Capacitive Loading

A novel and compact elliptic‐function bandpass filter is proposed in this letter. The techniques of slot etching and the addition of open stubs are applied to enhance the self‐inductance and self‐capacitance of hexagonal open‐loop resonators. Thus, size reduction and improved transmission performance are obtained. Compared to the performance of the conventional design, the central frequency and insertion loss are reduced by 28% and 3.1 dB, respectively. Measurements show that the proposed filter has a fraction bandwidth of 23% at the central frequency of 1.84 GHz, and its insertion loss in the passband is less than ?1.5 dB. The bandpass filter occupies only 12 mm×21.2 mm (approximately 0.24λ_g×0.14λ_g).     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

Mobile GPS carrier phase tracking using a novel intelligent dual‐loop receiver

Carrier phase information is necessary for accurate measurements in global positioning system (GPS) applications. This paper presents a novel intelligent GPS carrier tracking loop with variable‐bandwidth characteristics for fast acquisition and better tracking capability in the presence of dynamic environments. Our dual‐loop receiver is composed of a frequency‐locked loop‐assisted phase‐locked loop structure, the fuzzy controllers (FCs), and the ATAN discriminator functions. The soft‐computing FCs provide the time‐varying loop gains to perform accurate and reliable control of the dual‐loop paradigm. Once the phase dynamic errors become large under kinematic conditions, the fuzzy loop gains increase adaptively and achieve rapid acquisition. On the other hand, when the tracking errors approach zero in the steady state, the loop gains decrease and the corresponding dual‐loop receiver returns to a narrowband system. Four types of carrier phase signals, i.e. phase offset, decaying sinusoidal phase jitter, frequency offset, and frequency ramp offset, are considered to emulate realistic mobile circumstances. Simulation results show that our proposed receiver does achieve a superior performance over conventional tracking loops in terms of faster settling time and wider acquisition range while preventing the occurrence of cycle slips. Copyright © 2008 John Wiley & Sons, Ltd.     

软件无线电中多模式载波同步技术的研究

首先简要分析了锁相环和锁频环的基本原理,引出了锁相环的鉴频辅助方法,然后对其实现方法进行了研究,仿真结果表明:本文所研究的载波同步方法不仅兼容性强,而且能够解决同步速度与精度之间的矛盾.     

新型频率辅助高精度数字锁相环的设计与实现

针对某深空USB（统一S频段）测控系统的高精度侧音测距需要,提出了一种基于频率测量和二次混频的高精度数字锁相环实现方案。其由高精度测频、数字混频、滤波抽取、二阶数字锁相环等模块组成。采用VHDL可编程语言,基于可编程逻辑器件XC4VLX100平台,实现了所提出的方案。实验室环境下,测得实际环路等效噪声带宽达到30Hz,输入载噪比为25dB·Hz时环路工作稳定。测试结果表明,该高精度数字锁相环达到了系统设计要求,满足了相关参数指标。     

10Gb/s时钟数据恢复电路行为级模型研究

研究了超高速（10Gb／s）NRZ码时钟数据恢复电路的行为级建模,并采用TSMC 0．18 μm CMOS工艺进行了电路级仿真。     

New Matrix Loop Algebra and Its Application

A new matrix Lie algebra and its corresponding Loop algebra are constructed firstly, as its application, the multi-component TC equation hierarchy is obtained, then by use of trace identity the Hamiltonian structure of the above system is presented. Finally, the integrable couplings of the obtained system is worked out by the expanding matrix Loop algebra.