Spectral estimates for saddle point matrices arising in weak constraint four‐dimensional variational data assimilation

We consider the large sparse symmetric linear systems of equations that arise in the solution of weak constraint four‐dimensional variational data assimilation, a method of high interest for numerical weather prediction. These systems can be written as saddle point systems with a 3 × 3 block structure but block eliminations can be performed to reduce them to saddle point systems with a 2 × 2 block structure, or further to symmetric positive definite systems. In this article, we analyse how sensitive the spectra of these matrices are to the number of observations of the underlying dynamical system. We also obtain bounds on the eigenvalues of the matrices. Numerical experiments are used to confirm the theoretical analysis and bounds.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

一种大尺度二维直线度精密测量的新方法

本文提出了一种远距离、大范围二维直线度测量的新方法．该方法采用特殊设计的十字线准直激光器及线阵CCD，通过特殊的光学系统结构设计，能在0-20m距离内连续测量，直线度范围可达70mm，精度优于0．1mm，实际测量结果表明，该方法可适应野外作业环境。     

平面阵列波导光栅波导模式参量的分析

用周期波导的方法分析平面阵列波导光栅(AWG)的本征方程及波导模式参数,结果表明波导传播常数是带状分布的,与波导间隔有关。分析结果对器件的优化设计有一定的指导意义。     

一般阵列误差情况下信号二维方向角估计

针对均匀圆阵存在一般阵列误差的情况,提出一种信号二维方向角估计方法.基于均匀圆阵的阵列流形和阵列输出的协方差矩阵,采用加权总体最小二乘法估计信号二维方向角.并给出了解整周期性模糊的方法.计算机仿真表明了此方法估计精度高,对阵列误差鲁棒性强,并且各项性能都接近于CRB.     

Wavelength and Waveband Assignment for Ring Networks Based on Parallel Multi‐granularity Hierarchical OADMs

In this paper we study the optimization issues of ring networks employing novel parallel multi‐granularity hierarchical optical add‐drop multiplexers (OADMs). In particular, we attempt to minimize the number of control elements for the off‐line case. We present an integer linear programming formulation to obtain the lower bound in optimization, and propose an efficient heuristic algorithm called global bandwidth resource assignment that is suitable for the design of large‐scale OADM networks.     

MIMO系统的约束广义预测控制

讨论了输出终端带不等式约束情形的多输入多输出系统，说明了这些约束可以通过修改输入柔化系数而使其得以满足，在柔化系数的选择范围确定过程中，为了避免矩阵求逆，采用利用已知数据辨识参数的方法来确定柔化系数，从而使得问题简化。降低了计算量且加快了收敛速度。     

用DSP实现多目标实时跟踪

介绍了在 TMS3 2 0 C62 0 3上实现 4个目标的快速跟踪技术。为了提高实时性和精确度 ,采用线性汇编优化实现。1个 3 2 0× 160主窗口的 DSP平均处理时间为 2 m s,3个 60× 60副窗口的 DSP平均处理时间各为 0 .4ms,实现了复杂背景下低对比度目标的快速跟踪。实验结果证明跟踪效果良好 ,解决了以前窗口开不大、跟踪速度慢的问题     

二单元DPCA在机载相控阵雷达AMTI中的应用

二单元偏置相位中心天线技术 (DPCA)在机载相控阵雷达自适应动目标指示 (AMTI)中占有重要地位 ,其原理在很多文献中都有讨论。文中主要提出了将二单元DPCA应用到机载相控阵雷达的具体方法和实验步骤 ,针对接收数据是M×N矩阵的情况 ,分析了数据降维变换的具体过程 ,并从仿真结果中得到有效性证明。该方法对DPCA在实际工程中的应用具有重要参考价值     

一种CMOS静态双沿顺序脉冲发生器的设计

提出一种基于CMOS技术的静态双沿顺序脉冲发生器结构。他是由以基于CMOS二选一选择器的电平型触发器构成的记忆单元和一个与门阵列组成的转译单元构成的。与门阵列的转译单元使顺序脉冲发生器在时钟上升沿和下降沿处均能输出移位脉冲,从而形成双沿触发的功能。仿真验证其功能正确,且根据分析该结构不仅能够节省芯片面积,还可以大大减小芯片的功耗。