基于PSCAD/EMTDC的轻型直流输电系统设计

与传统的高压直流输电系统相比,轻型直流输电系统(HVDC Light)采用绝缘栅双极晶体管(IGBT)作为功率开关器件,能够对有功功率和无功功率进行独立的控制,具有调节迅速,稳定性高等优点。在研究轻型直流输电技术的工作原理和控制方法的基础上,设计了一个轻型直流输电系统,并在电磁暂态程序PSCAD/EMTDC环境下建立仿真模型,仿真实验结果验证了系统参数选择的合理性和控制方法的有效性。     

On chip novel video streaming system for bi-network multicasting protocols

In the past three decades, tremendous Ethernet-related research has been done, which has led to today's ubiquitous Ethernet technology. On the other hand, with the emergence of new network needs, a new protocol, the IEEE 1394 standard serial bus (or Firewire) was introduced. Firewire is suitable for high-quality audio/video applications which do not perform well in the best-effort-based Ethernet technology. However, since Firewire is a serial bus, it has harsh cable length limitations as compared to Ethernet capabilities.In this paper, we present a novel on-chip system that receives Firewire video and transmits it in multicast mode using Ethernet protocol. A major advantage of this novel system is to utilize the existing Ethernet infrastructure to extend the range of Firewire video streaming to reach remote nodes and make it even accessible to nodes with a single Ethernet interface. This will have tremendous impact on Firewire applications such as deploying Firewire cameras in big-scale security-sensitive buildings or industrial facilities with image-based remote quality control.This novel chip utilizes the concept of Ethernet multicasting transmission mode for video streaming. The proposed chip design converts the IEEE 1394 isochronous traffic to the Ethernet multicast frame format via two off-chip asynchronous write and read buffers.The goal of this research is to design an On Chip Novel Video Streaming System that avoids performance bottlenecks in the software protocol conversion of these two important network protocols. The author decided to study these two networks because of their broad use and cable power provisioning capabilities. The novel system design is implemented using a customized field programmable gate array (FPGA), which enables the integration of various system components on one chip. The designed prototype is studied using both network monitoring tools and analytical techniques, to verify its function and compare it with the existing approaches.Performance measures show that the On Chip Novel Video Streaming System consumes less than 21 mW of power for 100 Mbps and 82 mW of power for 1 Gbps, and utilizes 57% of a Xilinx Spartan 2-100E-6FT256 FPGA resources. Hence, it is possible to incorporate further extensions. Experimental results show that 88% of the network utilization can be achieved, due to the use of the customized, FPGA-based design of bi-network traffic conversion.     

Characteristics of GdGaO grown by MBE

Ga₂O₃/GdGaO dielectric stacks have been grown on GaAs for MOSFETs. This paper highlights variations in the characteristics of GdGaO as the Gd flux, Ga₂O flux and substrate temperature are changed. The growth rate, composition, crystallinity are discussed and the sheet resistance of final MOSFET structures are presented. The Gd compositional variation with depth is examined using Rutherford back scattering (RBS) and electron energy loss spectroscopy (EELS).     

多通道实时数字鉴相技术的FPGA实现

数字式干涉仪测向体制中的相位差信息在频域上提取,与传统的在时域提取相比能大大提高低信噪比条件下鉴相精度及对信号的适应能力。利用相位差信息的频域数字提取方法,实现了单片FPGA完成多通道相位信息的提取。与传统的计算机实现和DSP实现相比,不但提高了速度,而且设备量小,具有明显的优势。     

Priority Encoder Based on DNA Strand Displacement

The slow development of traditional computing has prompted the search for new materials to replace silicon-based computers.Bio-computers,which use molecules as the basis of computation,are highly parallel and in-formation capable,attracting a lot of attention.In this study,we designed a NAND logic gate based on the DNA strand displacement mechanism.We assembled a molecular calculation model,a 4-wire-2-wire priority encoder logic circuit,by cascading the proposed NAND gates.Different concentrations of input DNA chains were added into the system,resulting in corresponding output,through DNA hybridization and strand displacement.Therefore,it achieved the function of a priority encoder.Simulation results verify the effectiveness and accuracy of the molecular NAND logic gate and the priority coding system presented in this study.The unique point of this proposed circuit is that we cascaded only one kind of logic gate,which provides a beneficial exploration for the subsequent development of complex DNA cascade circuits and the realization of the logical coding function of information.     

数字阵列雷达接收链路的噪声检测方法

在数字阵列雷达中,接收通道的性能直接影响着雷达整机的探测性能。接收链路中有模拟电路、数字电路,每个环节都可能出现噪声异常抬高现象,造成接收链路的性能指标下降,影响雷达系统的性能。文中依据雷达接收链路架构以及接收链路的噪声组成,分析了链路中噪声异常产生的影响,并以模/数(A/D)芯片噪声异常为例对雷达性能影响进行了仿真。基于噪声检测原理和器件特征,给出了数字阵列雷达接收链路噪声检测的两种方法,包括绝对值判别法和通道间比幅法,可实时定位故障链路,保证雷达任务顺利进行。