A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Chirp Control of an Electroabsorption Modulator to be used for Regeneration and Wavelength Conversion at 40 Gbit/s in All-Optical Networking

Chirp control to produce low or negative values of chirp at the output of an electroabsorption modulator (EAM) is an important mechanism for reducing the signal degradation due to chromatic dispersion in high-speed transmission over standard single-mode fibre. An analytical model for the chirp performance of an EAM capable of optical regeneration and simultaneous wavelength conversion operating at 40 Gbit/s is derived. A chirp control approach is identified using this model by exploring the tradeoff between the α-parameter describing the chirp factor (based on the nonlinear absorption coefficients) and bias voltage requirements of an EAM. In particular, an optimum range of bias voltage is determined to ensure reduced chirp operation when a two-tone signal (i.e., comprised of bias and modulating voltages) is applied to the EAM. It is also demonstrated for large signal operation at 40 Gbit/s that the optimum range of reverse bias voltage is between 0 and 2 V to obtain low values for the chirp factor (between +1 and −2) in order to facilitate the necessary chirp control in all-optical networking. In addition, it is identified that at 40 Gbit/s higher positive values of the second- and third- order nonlinear coefficients of chirp must be avoided when operating at reverse bias voltages less than 1 V.     

Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing

To facilitate test vector generation for high-speed circuits, we present the design and circuit simulation of parallel pseudorandom number generators in GaAs technology. These PRNGs are based on hybrid cellular automata (CA) in which mixtures of local rules are employed in one dimensional arrays, with minimal delay due to having only local wiring between neighboring cells. HSPICE simulations of these circuits demonstrate that they operate at a clock frequency above 1 GHz. Delay simulations indicate that GaAs PRNGs based upon linear feedback shift registers, in contrast with hybrid CAs, exhibit a degradation in clock frequency due to the effects of global interconnects, and that this degradation increases with the register length.This work was supported by Micronet, by the Canadian Microelectronics Corporation, and by the Natural Sciences and Engineering Research Council of Canada.     

弱激波冲击无膜重气柱和气帘界面的实验研究

研制了一个改进的激波管设备,对马赫数为1.2的弱激波冲击作用下空气中SF6气柱和气帘界面的演变过程进行了初步的实验研究。通过设计激波管实验段、烟雾发生器、气体箱、进气吸气系统和激波管尾段,控制混合气体中SF6的峰值浓度和初始气流速度,建立了稳定、可重复的无膜气柱和气帘初始界面形成技术。利用高速摄影技术,在水平面内观测了气柱和气帘的初始界面图像,沿垂直方向观测了界面RM(Richtmyer-Meshkov)不稳定性的演变过程。气柱演变图像显示了典型的对涡结构,气帘演变图像显示了早期的多蘑菇形结构和后期的相邻波长干扰效应。图像后处理表明,气柱的高度和宽度、气帘的宽度均随时间单调增加,且宽度比高度增加快得多。从二维涡量动力学方程出发,对图像中涡的演变过程进行了初步解释。     

偏振态的高速实时测量方法的研究

偏振态的测量在光通信领域有着重要的作用,因此越来越受到人们的关注。在分析现有方案的基础上,推导出了新的斯托克斯计算公式,以此公式为依据提出了一种能对高速变化的偏振态进行实时测量的新方案,并对可能产生的误差因素进行了分析。给出了制作实用化测量模块所要达到的器件要求和制作工艺。     

基于双向PWM变换器的微燃机发电系统起动／发电控制研究

针对微型燃气轮机（微燃机）发电系统的特点,建立了以电压型双向脉宽调制（PwM）变换器为功率变换装置的起动／发电控制模型。微型燃气轮机发电系统起动时,采用矢量控制;发电运行时,采用电压外环电流内环的双环PWM整流控制。仿真实验结果表明：起动时,高速永磁同步电机（PMSG）采用矢量控制比速度开环控制性能更优,减少了起动时间,满足快速起动的要求;发电运行时,与二极管整流相比,PWM整流能使交流侧电流跟踪发电机的感应电动势,功率因数约为1,降低了发电机侧的电流谐波,即减少了谐波热。同时保证了发电机在一定宽速范围内,输出直流电压稳定,并且在起动一发电过渡转换过程中,直流母线电压降落后,快速恢复为稳定值,满足平滑转换的要求。     

掺铒光纤放大器自动测试系统的研究

为了提高掺铒光纤放大器(EDFA)的生产效率,文章作者设计了能快速测量EDFA各项性能参数的自动测试系统.该系统由一台计算机同时控制多台光放大器测试仪器,并能产生详尽的测试数据图表.实验证明,该系统的测试精度较高,能够充分满足用户的测试要求.     

RLC传输线的精确矩模型及其在互连线网时延估计中的应用

快速估计互连线网的信号传输特性是VLSI设计中的重要问题,矩匹配是目前的主要方法.本文给出了获得RLC传输线精确矩模型的一个简单方法,避免了以往方法复杂的推导.文中还提出了互连线时延估计的一个新方法,这一方法不仅可用于目前通常的二阶模型,还可对高阶模型进行估计.     

大容量散射调制解调器设计方案探讨

简要介绍了近年来国外大容量散射通信的发展水平和主要技术特点,并根据我国现有的技术基础和对大容量散射通信的需求背景等因素对我国的16Mbps大容量散射调制解调器和编解码器的设计方案进行了探讨。最后分别给出了16Mbps大容量散射通信系统在白高斯噪声信道、信道模拟器及实际野外信道上的测试结果,从而证实了大容量散射调制解调器在采用自适应判决反馈均衡及Turbo乘积码的技术体制下,具备了可靠传输16Mb/s的数字信号的能力。     

10Gbit/s高速串行通道的Hspice仿真研究

随着光传输技术的飞速发展,信号传输速率已经突破Gbit/s级,高速通道的仿真分析已成为系统开发成功与否的关键一环.文章简要介绍了Hspice仿真的基本原理和基本方法,并详细讨论了基于Hspice软件的高速串行通道仿真方法,通过仿真眼图的对比结果说明影响高速通道性能的几个关键环节以及改善通道特性的方法.