Interface features of ultrasonic flip chip bonding and reflow soldering in microelectronic packaging

Ultrasonic features in the bonding area are of interest for researchers in the field of microelectronic packaging. In this study, the interface characteristics of bonding were examined using an XD7100 X‐ray instrument and a transmission electron microscope (TEM). It was seen that bubbles were usually detected at the interfaces of the reflow‐soldered flip chip (FC), but they were not found at the interfaces of ultrasonically formed FC, and so ultrasonic FC bonding is more reliable than reflow soldering. The strong mechanical effect of ultrasonic vibration activates the dislocations in the crystalline metal lattice. Dislocation diffusion is more prominent than crystal diffusion when the temperature is relatively low during ultrasonic bonding, and therefore the processes of ultrasonic bonding enhance by several orders of magnitude. This indicates that the mechanism of ultrasonic bonding is different from the melting mechanism of reflow soldering. Copyright © 2007 John Wiley & Sons, Ltd.     

Kinetics of copper and high Pb/high Sn bilayered Pb-Sn solder interactions

Use of bilayered Pb-Sn solders consisting of high Sn and high Pb solder compositions is an option for joining chips to organic substrates at lower temperatures in which the high Sn solder is deposited onto Cu pads on the substrates. In this work interactions between the two-layered solder and copper pads during the reflow operation have been studied for both flip chip and Ball Grid Array (BGA) applications. It has been observed that Sn from the high Sn solder migrates faster at the edges along the surface of the high Pb solder than at the interior, resulting in a non-uniform Sn concentration along the Cu-solder interface. The thickness of the intermetallic compound formed due to the interaction of Cu and Sn has also been found to be non-uniform along the solder-Cu interface. This has been attributed to the variation in the Sn concentration of the solder adjacent to the Cu pads at different positions. The intermetallic compound growth rate has been explained using a model based on Sn diffusion into copper.     

动态扰动辅助的串行抵消双比特翻转Polar译码算法

针对串行抵消翻转译码算法（Successive Cancellation Flip,SCF）受限于单比特翻转而性能提升有限问题,提出了一种双比特翻转译码算法（Successive Cancellation Flip with 2 Bits,SCF2）。针对SCP算法扰动方差初始值固定的问题,设计了一种扰动方差可随码长和码率变化的改进SCP算法。在此基础上,结合翻转和扰动机制,提出了一种动态扰动辅助的串行抵消双比特翻转（Dynamic Perturbation-Aided SCF2,DPA-SCF2）译码算法,并对其译码复杂度和性能进行了分析。仿真结果显示,相比于列表长度为4的循环冗余校验辅助串行抵消列表（Cyclic Redundancy Check Aided Successive Cancellation List,CA-SCL）译码算法,所提算法最大可获得约0.5 dB的性能增益。     

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip‐Flops

This paper presents a novel test point insertion (TPI) method for a pseudo‐random built‐in self‐test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip‐flops to drive control test points instead of adding extra dedicated flip‐flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip‐flops from being replaced by functional flip‐flops. This paper proposes a logic cone analysis–based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop‐flops for replacing dedicated flip‐flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip‐flops.     

锁存器和触发器振荡问题分析

锁存器和触发器是时序逻辑电路的基本构件,而S-R锁存器是锁存器和触发器的构成基础。借助电路输入输出时序关系,本文探析了S-R锁存器出现振荡的本质原因,这一探讨有助于避免振荡问题的产生,也有助于数字系统的可靠性设计。     

Codimension one and two bifurcations of a discrete stage-structured population model with self-limitation

In this paper, the bifurcations of a discrete stage-structured population model with self-limitation between the two subgroups are investigated. We explore all possible codimension-one bifurcations associated with transcritical, flip (period doubling) and Neimark-Sacker bifurcations and discuss the stabilities of the fixed points in these non-hyperbolic cases. Meanwhile, we give the explicit approximate expression of the closed invariant curve which is caused by the Neimark-Sacker bifurcation. After that, through the theory of approximation by a flow, we explore the codimension two bifurcations associated with 1:3 strong resonance. We convert the nondegenerate condition of 1:3 resonance into a parametric polynomial, and determine its sign by the theory of complete discrimination system. We introduce new parameters and utilize some variable substitutions to obtain the bifurcation curves around 1:3 resonance, which are returned to the original variables and parameters to express for easy verification. By using a series of complicated approximate identity transformations and polar coordinate transformation, we explore 1:6 weak resonance. Moreover, we calculate the two boundaries of Arnold tongue which are caused by 1:6 weak resonance and defined as the resonance region. Numerical simulations and numerical bifurcation analyzes are made to demonstrate the effective of the theoretical analyzes and to present the relations between these bifurcations. Furthermore, our theoretical analyzes and numerical simulations are explained from the biological point of view.     

基于倒扣技术的24GHz混合集成平衡混频器

介绍采用混合贴装倒扣二极管技术制造的新型24GHz平衡混频器，并对该混频器进行设计、仿真、加工和测试，它能提供中频100kMz时小于10dB的变频损耗，本振与信号之间优于35dB的隔离度，其结构特点利于大批量、低成本生产，适合汽车电子系统的需求。     

一种低成本倒装芯片用印刷凸焊点技术的研究

利用化学镀底部金属化层结合丝网印刷制作凸焊点的技术,通过剪切实验得到了凸焊点的剪切强度,用电子显微镜对失效表面进行了分析研究,应用SEM及EDAX分析了凸焊点的组织结构与成分变化,对热老炼后凸焊点的强度变化进行了研究。结果表明凸焊点内部组织结构的变化是剪切失效的主要原因。经X光及扫描声学显微镜检测,表明组装及填充工艺很成功。对已完成及未进行填充的两种FCOB样品进行热疲劳实验对比,发现未进行填充加固的样品在115周循环后出现失效,而经填充加固后的样品通过了1 000周循环,表明下填料明显延长了倒装焊封装的热疲劳寿命。     

Development of under bump metallizations for flip chip bonding to organic substrates

Several under bump metallization (UBM) schemes using CuNi alloys as the solderable layer were investigated. Nickel slows down dissolution of the UBM into the solder and formation of intermetallics during reflow. To study the intermetallic reaction, CuNi foils of different concentrations were immersed in a eutectic PbSn solder bath for reaction times ranging from 30 seconds to 30 minutes. It was observed that when 10% and 20% Ni is added into copper, the intermetallic forms a continuous layer, instead of the discrete scallops seen in pure Cu/solder interfaces. However, the thickness of the intermetallic remained about the same. For 30% and 45% Ni alloys a definite decrease in the intermetallic thickness was observed compared to the lower Ni alloys. Actual under bump metallizations were also made on Si wafers to study the reactions when there is a limited supply of CuNi available. Cr or Ti was used as the adhesion layer, and the solderable layer was a copper-nickel alloy, instead of pure copper used in the conventional UBM scheme. The metal layers were deposited on a wafer by evaporation and patterned into contact pads. Eutectic PbSn solder balls were reflowed on top of the pads. SEM micrographs of the intermetallic that forms at the UBM/solder interface show the refining effect of Ni in the interfacial microstructure. Since nickel metallizations often have high stresses, stress in the UBMs was measured by the wafer curvature method. Stress vs Ni content plots show that while stresses increase somewhat with the Ni content, the adhesion layer under the CuNi layer has a much larger effect on the stress. UBMs with Cr/CrCu adhesion layer had stresses ranging from about 300 to 600 MPa, while the stresses in UBMs with Ti/TiNi layers were between 70 and 350 MPa.     

Electroless Ni/Au Bump on a Copper Patterned Wafer for the CMOS Image Sensor Package in Mobile Phones

Wafer bumping technology using an electroless Ni/Au bump on a Cu patterned wafer is studied for the flip chip type CMOS image sensor (CIS) package for the camera module in mobile phones. The effect of different pretreatment steps on surface roughness and etching of Cu pads is investigated to improve the adherence between the Cu pad and the Ni/Au bump. This study measures the shear forces on Ni/Au bumps prepared in different ways, showing that the suitable pretreatment protocol for electroless Ni plating on Cu pads is “acid dip followed by Pd activation” rather than the conventional progression of “acid-dip, microetching, and Pd activation.” The interface between the Cu pad and the Ni/Au bump is studied using various surface analysis methods. The homogeneous distribution of catalytic Pd on the Cu pad is first validated. The flip chip package structure is designed, assembled, and tested for reliability. The successful flip chip bonding in the CIS package is characterized in terms of the cross-sectional structure in which the anisotropic conductive film (ACF) particles are deformed to about 1.5 μm in diameter. The experimental results suggest that electroless Ni/Au can be applied to the flip chip type CIS package using Cu patterned wafers for high mega pixel applications.