基于IPv6测试实验室的设计与实现研究

随着网络技术的发展,IPv4地址的耗尽,惠州城市职业学院在建设传统IPv4实验室的基础上,增加了IPv6测试实验室建设,本文主要研究了惠州城市职业学院的IPv6测试实验室的建设问题,在测试实验室中配置和测试Win2008 Server和win7的IPv6协议。通过本文的研究,完成一系列任务,即可从一个IPv4-only的测试实验网络架构,到混合的IPv4-only和IPv6-capable的架构,到最后IPv6-only的设施。本文IPv6测试实验室的建设将辅助开发ipv6应用程序或把现有程序修改为支持IPv4和IPv6的应用程序。     

基于FPGA的芯片功能性验证自动化实现

针对传统半导体设计流程中对MCU芯片进行功能性验证时涉及到多个芯片之间的互联,手工操作连接十分烦琐且易出现错误,介绍了一种基于FPGA的MCU引脚自动互联的设计与实现.介绍了MCU模块功能性验证自动化实现的概念,从硬件逻辑角度给出了一种解决方法,并且从FPGA模块设计、功能仿真和系统实现等方面,证明了新的测试方法不但降低了人为操作错误的可能性,而且提高了模块功能验证的覆盖率和验证效率,大大缩短了产品的上市时间.     

集成电路测试系统软件的设计及实现

本文主要展示了集成电路测试系统软件的基本功能及其核心部分的实现方法。先介绍了集成电路测试系统硬件的建模方法,然后在硬件建模的基础上讲述了集成电路软件的结构及设计方法。着重介绍了流程图测试程序转化为文本测试程序的方法以及对文本测试程序的编译方法。用户只需要根据测试流程编写流程图即可以实现测试程序的编写,实现对IC的测试,提高了开发效率。该软件系统具有和硬件系统低耦合性,当向集成电路测试系统添加删改硬件时,不需要修改太多的软件内容即可以正常工作,通用性较好。     

一种新型高量程微加速度传感器侵彻测试

设计一种新型高量程压阻式微加速度传感器.并将其应用于对铜靶和混凝土靶进行100000 g以上的侵彻测试.实验结果表明,该传感器在侵彻钢靶具有良好的抗过载能力.对实测过栽时程曲线进行系统分析,结果表明该传感器与988传感器的侵彻过载数据基本吻合:侵彻混凝土靶时出现传感器粱断裂现象.需进一步从封装方面改进.     

基于正交试验和有限元计算的优化设计方法

介绍了基于正交试验和有限元计算的模态优化方法。针对影响结构件模态值的主要影响因素进行优化组合,得到结构件的最大模态值。应用该方法对某雷达反射面进行分析验证,为复杂设备的优化设计提供了基础性的设计方法。     

基于分类树的雷达软件测试用例设计

现代雷达软件测试由于软件规模越来越大,利用常规的组合覆盖方法测试各功能单元工程上越来越不现实。文章针对分类树方法设计测试用例产生大量冗余测试用例的缺陷,提出了在分类树方法生成的用例集基础上,利用正交试验设计法对其进行精简优化,以提高测试效率。实验结果表明,基于正交试验设计法的测试用例优化,可以有效减少冗余测试用例,节省测试资源和成本,具有一定的工程应用价值。     

GPS轨迹测量系统在导弹飞行试验中的应用

空空导弹研制需要一系列空中系留飞行试验,以解决导弹制导系统对真实目标的截获跟踪能力。传统的系留试验由于地面试验人员无法实时掌握靶机和目标机的动态,给飞行试验结果造成了很大的不确定性;本系统利用日益广泛使用的GPS全球定位技术,从载机的导弹产品和目标机GPS吊舱接收下传的GPS信息,实时解算出目标机相对于载机位置、速度等信息,显示在数据处理软件上,从而使地面试验人员实时获取载机和目标机的相关信息,为试验指挥提供了可靠数据;实际应用结果表明,该系统大大提高了系留试验的成功率和导弹截获概率,为飞行试验节约了试验经费和时间,创造了良好的经济效益。     

网络化虚拟仪器的构思及实现

Internet的迅速发展及在许多科研领域的应用,正在改变着人们传统的思维模式,将Internet引入到测试领域邓所谓的网络化测试有望得以实现,文章阐述了现代仪器仪表发展的趋势为：网络就是仪器”[1]的思想,重点介绍了网络化虚拟仪器的概念及组建构思。     

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters. Yolanda Lechuga received a degree in Industrial Engineering from the University of Cantabria (Spain) in April 2000. Since then, she has been collaborating with the Microelectronics Engineering Group at the University of Cantabria, in the Electronics Technology, Systems and Automation Engineering Department. Since October 2000 she has been a post-graduate student, to be appointed as lecturer at this university, where she is working in her Ph.D. She is interested in supply current test methods, fault simulation, BIST and design for test of mixed signal integrated circuits. Román Mozuelos received a degree in Physics with electronics from the University of Cantabria, Spain. From 1991 to 1995 he was working on the development of quartz crystal oscillators. Currently, he is a Ph.D. student and an assistant teacher at the University of Cantabria in the Department of Electronics Technology. His interests include mixed-signal design and test, fault simulation, and supply current monitoring. Miguel A. Allende received his graduate degree in 1985 and Ph.D. degree in 1994, both from the University of Cantabria, Santander, Spain. In 1996, he became an Assistant Professor of Electronics Technology at the same Institution, where he is a member of the Microelectronics Engineering Group at the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. His research interests include design of VLSI circuits for industrial applications, test and DfT in digital VLSI communication circuits, and power supply current test of mixed, analogue and digital circuits. Mar Martínez received her graduate degree and Ph.D. from the University of Cantabria (Spain) in 1986 and 1990. She has been Assistant Professor of Electronic Technology at the University of Cantabria (Spain) since 1991. At present, she is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. She has participated in several EU and Spanish National Research Projects. Her main research interest is mixed, analogue and digital circuit testing, using techniques based on supply current monitoring. She is also interested in test and design for test in digital VLSI circuits. Salvador Bracho obtained his graduate degree and Ph.D. from the University of Seville (Spain) in 1967 and 1970. He was appointed Professor of Electronic Technology at the University of Cantabria (Spain) in 1973, where, at present, he is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. He has participated, as leader of the Microelectronics Engineering Group at the University of Cantabria, in more than twenty EU and Spanish National Research Projects. His primary research interest is in the area of test and design for test, such as full scan, partial scan or self-test techniques in digital VLSI communication circuits. He is also interested in mixed-signal, analogue and digital test, using methods based on power supply current monitoring. Another research interest is the design of analogue and digital VLSI circuits for industrial applications. Prof. Bracho is a member of the Institute of Electrical and Electronic Engineers.     

Structural Fault Based Specification Reduction for Testing Analog Circuits

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.