Mechanisms of martensitic transformations in boron nitride and conditions of their development

Abstract

The dependence of the pressure threshold of martensitic transformations on the disordering degree of starting structures is considered for graphite-like BN into diamond-like BN modifications transitions. The effect of loading conditions on transformation mechanisms of rhombohedral BN into zinc blende or wurtzite modifications is analyzed also. Analytical relations obtained allow to explain the experimental data and to predict a behavior of various graphite-like structures under different p, T conditions.     

Physical phenomena affecting performance and reliability of 4H-SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300 A/cm². However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H-SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N-P-N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.     

More non-semigroup Lie gradings

This note is devoted to the construction of two very easy examples, of respective dimensions 4 and 6, of graded Lie algebras whose grading is not given by a semigroup, the latter one being a semisimple algebra. It is shown that 4 is the minimal possible dimension for such graded Lie algebras.     

高可用群集多处理技术的原理、规划及配置

在金融、通信等服务领域必须保证关键性业务对外稳定、持续地进行,群集技术(双机)为此提供了可靠的保证.首先介绍了群集的概念,然后基于IBM的AIX系统的高可用群集多处理技术(hacmp for aiz),对群集的网络、管理软件、单点故障、资源组接管策略等进行了详细分析,最后以一个客户端连接到应用、应用连接到数据库的3层客户/服务器(C/S)结构的金融应用系统为例,对群集的规划及配置进行了比较详细的讨论,并给出互相接管模式的双机配置规划和相关应用及数据库的起停脚本.     

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced. In addition, the consequences of the port restrictions (read-only or write-only ports) on the fault models and tests are discussed, together with the test strategy.     

电子设备故障诊断专家系统的设计

介绍了大型电子设备故障诊断专家系统的作用 ,阐述了该系统的软件设计、具体要求、功能及任务     

Extending Fault-Based Testing to Microelectromechanical Systems

As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.     

Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links

Characterization of catastrophic fault patterns (CFPs) and their enumeration have been studied by several authors. Given a linear array with a set of bypass links, an important problem is how to count the number of CFPs. Enumeration of CFPs for two link redundancy G={1,g} has been solved for both unidirectional and bidirectional link cases. In this paper, we consider the more general case of link redundancy G={1,2,…,k,g}, 2k<g. Using random walk as a tool, we enumerate CFPs for both unidirectional and bidirectional cases.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

新疆富蕴县萨尔布拉克金矿预测区断裂特征及其控矿规律

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