Design of testable sequential circuits by repositioning flip-flops

This paper presents a technique to enhance the testability of sequential circuits by repositioning flip-flops. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan flip-flops to break all cycles (except self-loops) as compared to the original circuit. Our technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit graph to minimize the number of flip-flops in the SCCs. A circuit graph has a vertex for every gate, primary input and primary output. If gatea has a fanout to gateb, then the circuit graph has an arc from vertexa to vertexb. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique in reducing the number of partial scan flip-flops.     

Modeling Custom Digital Circuits for Test

Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuck-faults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15–20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.     

一种并行决策树学习方法研究

提出一种并行的决策树学习方法。该方法首先将数据库分为若干个子部分,针对每个子部分分别进行决策树学习,优选分裂属性,再对各个决策树学习的结果综合,生成最终的树。在树上剪枝以降低分类错误率。通过在变压器绝缘故障诊断中的应用表明该方法有很强的学习能力和诊断速度,是一种有效的决策树学习方法。     

一种具有时序特征的告警关联规则挖掘算法

电信网络中各种频繁告警事件的发生通常具有一定的时序关系,据此提出了一种具有时序特征的告警关联挖掘算法。该方法解决了以往算法中无法发现告警序列之间时序关系的问题。其核心思想是在建立FP-tree时加入告警的时间特征,然后对FP-tree进行挖掘。实验证明,该算法能够快速、准确地从海量数据中挖掘出具有时序特征地关联规则。     

Thermal Annealing and Propagation of Shockley Stacking Faults in 4H-SiC PiN Diodes

Stacking faults within 4H-SiC PiN diodes are known to be detrimental to device operation. Here, we present electroluminescence (EL) images of 4H-SiC PiN diodes providing evidence that electrically and optically stimulated Shockley stacking fault (SSF) propagation is a reversible process at temperatures as low as 210°C. Optical beam induced current (OBIC) images taken following complete optical stressing of a PiN diode and that lead to a small number of completely propagated SSFs provide evidence that such defects propagate across the n–/p+ interface and continue to grow throughout the p+ layer. These observations bring about questions regarding the validity of the currently accepted driving force mechanism for SSF propagation.     

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.     

Growth of Fe on Ge(1 1 1) at room temperature studied by X-ray photoelectron diffraction

The growth of ultrathin Fe films of various coverages on Ge(1 1 1) at room temperature using molecular beam epitaxy (MBE) was studied via X-ray photoelectron diffraction (XPD or XPED) together with low energy electron diffraction (LEED) and X-ray photoelectron spectroscopy (XPS). All experimentally observed XPD patterns suggested local order structures of the Fe layers for all thicknesses studied. The short-range order of the resulting structures was found to be enhanced for thinner layers whereas the long-range order was gradually lost with increasing Fe thicknesses. At a very low coverage of 0.8 Å Fe and Ge tend to react to the partly ordered structure in which Fe atoms were located in local environments similar to those for higher Fe coverages. Comparison of theoretical and experimental XPD patterns, along with XPS results, showed that intermixing between Fe and Ge occurred during the pseudomorphic growth with a stacking fault near the interface for all Fe coverages under study. Nevertheless, small percentage of domains without the stacking fault was also found to coexist with those with the stacking fault by performing a quantitative analysis of a reliability factor R of the Fe2p pattern for 5.4 Å. The orientation changes of the Ge2p and Ge3d XPD patterns with Fe thickness were unambiguously explained in terms of their different dependencies on the overlayer thickness due to the different inelastic mean free path lengths used in the simulations. Also, Fe got increasingly enriched in the grown layers with increased Fe coverage. The resulting structures and intermixing are discussed in detail.     

基于MC68HC908KX2的ICG模块的应用研究

介绍了8位Motorola单片机MC68HC908KX2与同类产品相比的优点,重点叙述了ICG(内部时钟发生器)模块取代晶振构成的时钟电路在系统中所具有的不可替代的优势。针对汽车检测产品可靠性高、方便实用、抗干扰能力强等特点,利用MC68HC908KX系列单片机提供的ICG模块和少量外围元件,设计了宝马汽车故障检测子系统。给出了ICG模块详细的设置方法、系统的硬件原理图和部分原代码。该方法解决了单片机系统在工控领域恶劣电磁环境下易受干扰的问题。     

Misalignment Fault Prediction of Wind Turbines Based on Improved Artificial Fish Swarm Algorithm

A misalignment fault is a kind of potential fault in double-fed wind turbines. The reasonable and effective fault prediction models are used to predict its development trend before serious faults occur, which can take measures to repair in advance and reduce human and material losses. In this paper, the Least Squares Support Vector Machine optimized by the Improved Artificial Fish Swarm Algorithm is used to predict the misalignment index of the experiment platform. The mixed features of time domain, frequency domain, and time-frequency domain indexes of vibration or stator current signals are the inputs of the Least Squares Support Vector Machine. The kurtosis of the same signals is the output of the model, and the 3σ principle of the normal distribution is adopted to set the warning line of misalignment fault. Compared with other optimization algorithms, the experimental results show that the proposed prediction model can predict the development trend of the misalignment index with the least prediction error.     

遥感技术在孝丰-三门湾活动断裂调查中的应用——以杭州地区为例

遥感技术可以在宏观上对活动断裂及其构造特征进行全面的解译和识别．在区域遥感影像图制作和地质解译的基础上，采用增强和融合等图像处理方法，提高了遥感影像清晰度和解译精度，同时结合野外调查、测量以及断裂活动年代样品的采集和测定，对孝丰-三门湾断裂进行了详细的研究，查明了它的空间展布，并鉴定了活动时代和运动性质．研究结果表明，孝丰-三门湾断裂在杭州地区以挤压逆冲运动为主，兼有左旋走滑运动，并在各个地段和各个时期表现形式截然不同，影响了杭州南部地区地层沉积和构造演化．该断裂对杭州地区历史地震和现代地震具备一定的控制作用，可能在晚更新世以来有过活动．