一种软件代码精细分析技术

精细分析对提高关键软件的安全非常重要,并因计算量大而需要自动化.本文基于J M Voas的Fault/Failure概念模型及其PIE分析,提出一个实用的软件代码精细分析技术和工具.文中描述了软件代码精细分析的全过程,重点讲述“自动分析记录”的工作流程及执行、感染和传播这三个关键分析的概念性算法,并给出了工具的框架图解.此外还提出粒度可调思想,能调节分析的精度和范围,较好地解决了Fault/Failure模型的限制,拓展了用途.最后本文给出了一些具体的应用思路,如放置警报器、评估可靠性、配置资源、设计测试实例等,以及对面向对象软件测试的启发.     

The New Fault Tolerant Onboard Computer for Microsatellite Missions

1IntroductionWith the space technology developing,much moreCommercial-Off-The-Shelf(COTS)devices are used inmicrosatellites that are mostlylocatedin Low Earth Or-bit(LEO)[1~3].The COTS devices have relatively lowpower consumption,high processing performan…     

双机容错在医院信息系统中的设计与实现

双机容错是确保医院信息系统正常运转，防止数据丢失的重要技术。现针对目前多数综合性医院HIS系统中所面对的数据备份与安全策略的问题，结合医院的实际情况设计出了一套既实用又可靠的策略，并阐述了双机容错的具体设计与实现方法。     

紧致型小波网络在模拟电路故障诊断中的应用

提出了一种新的基于紧致型小波神经网络的模拟电路故障诊断方法。该法首先利用小波包变换对故障信号进行预处理,减少了紧致型小波神经网络的输入数目,简化了紧致型小波神经网络结构,然后对紧致型小波神经网络进行训练和测试。仿真试验表明,该方法比普通BP神经网络方法训练速度更快,诊断准确率更高,容错能力强,非常适用于模拟电路故障诊断。     

Detection of Defects Using Fault Model Oriented Test Sequences

This paper analyzes the possibilities and limitations of defect detection using fault model oriented test sequences. The analysis is conducted through the example of a short defect considering the static voltage test technique. Firstly, the problem of defect excitation and effect propagation is studied. It is shown that the effect can be either a defective effect or a defect-free effect depending on the value of unpredictable parameters. The concept of Analog Detectability Interval (ADI) is used to represent the range of the unpredictable parameters creating a defective effect. It is demonstrated that the ADIs are pattern dependent. New concepts (Global ADI, Covered ADI) are then proposed to optimize the defect detection taking into account the unpredictable parameters. Finally, the ability of a fault oriented test sequence to detect defect is discussed. In particular, it is shown that the test sequence generated to target the stuck-at faults can reasonably guarantee short defect detection till a limit given by the Analog Detectability Intervals.     

机械故障模糊诊断中模糊矩阵的可视化处理与分析

通过对机械故障诊断中的模糊矩阵及采用不同数学模型运算后的结果进行可视化处理,得到二维图谱和三维图谱,使故障与征兆之间的关系更加明确     

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults. Part of this work has ever appeared in the proceedings of Asian Test Symposium in 2003. Yu-Chiun Lin received his BS degrees in Electrical Engineering from National Central University in 2000, and MS degree from Electrical Engineering of National Tsing Hua University in 2002. Since then, he has been with Ali Corporation as a design engineer. His current interests include the design of USB controllers and imaging periperals. Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests include CMOS image sensor design, low-power memory design, power estimation, and fault diagnosis methodologies.     

Mathematical modeling of a steam generator for sensor fault detection

A dynamic model for a nuclear power plant steam generator (vertical, preheated, U-tube recirculation-type) is formulated as a sixth-order nonlinear system. The model integrates nodal mass and energy balances for the primary water, the U-tube metal and the secondary water and steam. The downcomer flow is determined by a static balance of momentum. The mathematical system is solved using transient input data from the Philippsburg 2 (FRG) nuclear power plant. The results of the calculation are compared with actual measured values. The proposed model provides a low-cost tool for the automatic control and simulation of the steam generating process. The “parity-space” algorithm is used to demonstrate the applicability of the mathematical model for sensor fault detection and identification purposes. This technique provides a powerful means of generating temporal analytic redundancy between sensor signals. It demonstrates good detection rates of sensor errors using relatively few steps of scanning time and allows the reconfiguration of faulty signals.     

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.