Desynchronization of large scale delayed neural networks

We consider a ring of identical neurons with delayed nearest neighborhood inhibitory interaction. Under general conditions, such a network has a slowly oscillatory synchronous periodic solution which is completely characterized by a scalar delay differential equation with negative feedback. Despite the fact that the slowly oscillatory periodic solution of the scalar equation is stable, we show that the associated synchronous solution is unstable if the size of the network is large.

     

具有时滞的细胞神经网络周期解与稳定性

本文研究了具有时滞的细胞神经网络周期解存在性和平凡解的稳定性问题 .利用 Lyapunov函数法并结合不等式分析技巧 ,我们首先证明了时滞细胞神经网络的解是有界的 ,然后建立了时滞细胞神经网络的周期解的存在准则 ,最后在时滞细胞神经网络有平衡点时 ,给出了神经网络系统的平衡点指数稳定的充分条件 .其结果推广了文 [7,8]的相应结果 .     

Conditions of asymptotic stability for cellular neural networks with time delay

In this paper, global asymptotic stability for cellular neural networks with time delay is discussed using a novel Liapunov function. Some novel sufficient conditions for global asymptotic stability are obtained. Those results are simple and practical than those given by P. P. Civalleri, et al., and have a leading importance to design cellular neural networks with time delay.     

一种基于小波多分辩率数据组合的文字水印方案

本文利用人眼视觉掩蔽特性,通过组合静态图像和文字水印对应方向上的小波细节子图数据,提出了一种基于小波多分辩率数据组合的在静态图像上嵌入文字水印的方案.借助于原始图像,能方便、可靠地检测出嵌入的文字水印.同时,对水印图像进行退化处理模拟实验表明,嵌入的文字水印具有很好的稳健性.     

Detection of Delay Faults in Memory Address Decoders

In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march test tactic. The proposed Transition Sequence Generator (TSG) generates an optimal transition sequence for sensitization of the delay faults in address decoders by Hayes's transformation on a reflected Gray code. It can be used for parallel Built-In Self-Testing (BIST) of high-density RAMs. We also present an efficient Design For Test (DFT) approach for immediate detection of the effects of the delay faults in the address decoders which does not change memory access time. It requires extra logic to be attached to the outputs of the address decoders. This DFT approach can be used to increase memory testability for both on-line and off-line testing of single- and multi-port RAMs.     

深亚微米VLSI电路中互连线的几何优化设计

基于三维 L aplace方程的 Silvaco Interconnect3D模拟程序数值解 ,对互连寄生电容进行了计算 ,其结果用于 0 .2 5μm CMOS技术互连延迟及串扰的 SPICE模拟中。模拟结果表明 ,基于W/ P=0 .3～ 0 .4的布线准则可以获得最优的互连延迟与串扰 (Crosstalk)特性 ,通过优化互连线及驱动管的几何尺寸可以显著地减小互连线的延迟及串扰噪声。     

H.323终端业务复用模型分析

本文提出了一种新的基于H 32 3多媒体会议系统的终端媒体流复用模型 ;对其进行了理论计算和计算机仿真 ;得到了模型中信元的循环时间、返回时间、缓冲区中平均数及时延的解析表达式 ;讨论了k2 ,λ2 ,μ等参数对循环时间、缓冲区中信元的平均时延的影响。结果表明通过调整相关参数 ,采用新的复用模型能够满足一定的时延和媒体流同步等实时性要求     

光纤延迟线编/解码器的研究

在光纤码分多址 ( CDMA)通信中 ,光纤延迟线编解码器是实现全光编解码的关键技术。对并行结构的光纤延迟线编解码器的原理及构造方法进行了分析 ,并给出相应的实验结果     

光纤延迟线编解码器的设计

光纤延迟线编码解器作为光码分多址系统时域编解码的基本器件,它起的作用是对光脉冲进行延时编码,同时也会给系统带来别的问题。例如：功率分离,延时损耗,温度抖动等。本文介绍了编码器的设计,同时对以上问题进行了分析,得出的结论包括：设计时必须考虑温度的影响,系统的损耗随着码重和用户数的增加而增加。这些可以对系统的设计提供一个参考。     

基于速度饱和的CMOS倒相器延迟模型

提出了一个新的小尺寸CMOS倒相器延迟模型,它考虑了速度饱和效应以及非阶梯的输入信号对延迟的影响并给出了倒相器快输入响应与慢输入响应的判据,模型计算结果与SPICEBSIM1模型的模拟结果吻合得很好.