Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction

In this paper, we propose techniques for fast cycle-approximate multi-processor SoC simulation with timed transaction level models and OS models. Cycle-approximate simulation with an abstract model is widely used for fast validation of a multi-processor SoC in early design stages. However, the performance gain of abstract-level simulation is limited by the overhead of synchronizing multiple concurrent processor/module simulators, which is inevitable in timed simulation. To reduce the synchronization overhead, we adopt the synchronization time-point prediction method, which consists of two phases: static code analysis and dynamic scheduling of synchronizations. In the static analysis phase before simulation, it estimates minimum execution time from every point in the code to the nearest synchronization point. Then, during simulation, it pessimistically predicts the synchronization time-points based on the estimates. The proposed approach targets fast cycle-approximate simulation of a system with delay annotated SW code and transaction level models of HW with dynamic behavior. We present, in this paper, techniques to analyze such abstract models of SW and HW and schedule minimal number synchronizations during cycle-approximate simulation of the models. Experiments show that the approach achieves orders of magnitude higher performance in cycle-approximate multi-processor SoC simulation.     

Web OS现状和发展趋势分析

随着智能操作系统和云计算技术的发展,Web OS作为一种新的以云服务为主的智能操作系统已经进入大家的视野。文章从Web OS的产品概念演变开始,分析Web OS早期和现阶段的产品特点,总结现阶段Web OS的发展现状以及将来的发展趋势。     

Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation

This paper presents a hardware/software co-design approachwhere different specification languages can be used in parallel, allowingeffective system co-modeling. The proposed methodology introduces a processmodel that extends the traditional spiral model so as to reflect the designneeds of modern embedded systems. The methodology is supported by an advancedtoolset that allows co-modeling and co-simulation using SDL, Statecharts andMATRIX_X, and interactive hardware/software partitioning. The effectivenessof the proposed approach is exhibited through two applicati on examples: thedesign of a car window lift mechanism, and the design of a MAC layer protocolfor wireless ATM networks.     

埋入无源元件从实验室到制造的发展

概述了埋入集成无源元件印制板以及它们的非真空加工和真空加工的选择,还讨论了埋入集成无源元件业务的拓展趋势。     

基于SX52BD单片机的以太网控制应用

通过对目前流行的嵌入式互联网方案进行分析,详细介绍了基于UBICOM公司生产的SX52BD单片机的因特网应用方案,并提出了以太网控制应用实例。     

Avalon总线与SOPC系统架构实例

介绍了可编程系统集成(SOPC)的基本概念和Avalon总线,着重描述了Avalon总线的内容和操作,利用SOPC Builder搭建了一个SOPC的实例,在Altera的Excalibur Nios开发板上进行了仿真验证。     

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidanceof over-constrained synchronization, and its simplified clocking requirements.However, analysis and optimization of self-timed systems under real-time constraintsis challenging due to the complex, irregular dynamics of self-timed operation.In this paper, we review a number of high-level intermediate representationsfor compiling dataflow programs onto self-timed DSP platforms, including representationsfor modeling the placement of interprocessor communication (IPC) operations;separating synchronization from data transfer during IPC; modeling and optimizinglinear orderings of communication operations; performing accurate design spaceexploration under communication resource contention; and exploring alternativeprocessor assignments during the synthesis process. We review the structureof these representations, and discuss efficient techniques that operate onthem to streamline scheduling, communication synthesis, and power managementof multiprocessor DSP implementations.     

TMS320C6201在嵌入式波束形成器中的应用

介绍了TMS320C6201在嵌入式波束形成器中的应用，讨论了嵌入式波束形成器的结构、算法、结合TMS320C6201的硬件条件优化数据搬移流程等问题，并最终给出波束形成器的EVM板仿真结果。     

基于DCT变换的内嵌静止图像压缩算法

提出了一种有效的基于离散余弦变换(DCT)的内嵌子带图像编码算法.Xiong等人提出的EZDCT算法采用零树结构实现了一种内嵌DCT编码器,且其性能优于JPEG.本文指出DCT的零树结构在内嵌DCT算法中并非很有效,同时提出了一种不依赖零树结构的简便、高效的内嵌DCT子带编码算法.实验结果表明本文算的压缩性能(PSNR)比EZDCT高约0.5~1.5dB,且接近当前最通用的内嵌小波SPIHT算法,在对某些图像压缩时还优于SPIHT算法.     

A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors

Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded processors. Unlike conventional general purpose processors, ASIPs and embedded processors typically run a single application and hence must be optimized extensively for this in order to extract maximum performance. Further, low power and low cost requirements of ASIPs may demand reuse of pipeline stages causing pipelines with complex structural hazards. In such architectures, exploiting higher ILP is a major challenge to the designer.Existing techniques deal with either scheduling hardware pipelines to obtain higher throughput or software pipelining—an instruction scheduling technique for iterative computation—for exploiting greater ILP. We integrate these techniques to co-schedule hardware and software pipelines to achieve greater instruction throughput. In this paper, we develop the underlying theory of Co-Scheduling, called the Modulo-Scheduled Pipeline (or MS-Pipeline) theory. More specifically, we establish the necessary and sufficient condition for achieving the maximum throughput in a given pipeline operating under modulo scheduling. Further, we establish a sufficient condition to achieve a specified throughput, based on which we also develop a methodology for designing the hardware pipelines that achieve such a throughput. Further, we present initial experimental results which help to establish the usefulness of MS-pipeline theory in software pipelining. As the proposed theory helps to analyze and improve the throughput of Modulo-Scheduled Pipelines (MS-pipelines), it is especially useful in designing ASIPs and embedded processors.