A mathematical model for an alloy solidification problem in the presence of an electric field

A one-dimensional mathematical model for a process of solidification of a binary alloy in the presence of an electric field is studied. A situation in which the thermal properties of each phase are different and the latent heat is non-zero is considered. A quasi-static approximation for the thermal and electric fields is used. Local existence and uniqueness of a classical solution to the resulting free boundary problem are proved for two kinds of boundary conditions. Moreover, under particular hypotheses, the monotonicity of the free boundary and the global existence of the solution is proved.

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Sommario Si studia un modello matematico unidimensionale per un processo di solidificazione di una lega binaria in presenza di un campo elettrico. Si considera una situazione in cui le proprietà termiche di ogni fase sono differenti e il calore latente è non nullo. Si usa una approssimazione quasi-statica per i campi elettrico e termico. Si dimostra l'esistenza locale e l'unicità di una soluzione classica per il problema di frontiera libera risultante con due tipi di condizioni di bordo. Inoltre si dimostra, sotto particolari ipotesi, la monotonia della frontiera libera e l'esistenza di soluzione globale.

     

金属电迁移测试过程中的电介质击穿效应

金属互连电迁移有断路失效和短路失效两种常规失效模式,其中短路失效是由于发生了析出效应.目前对电迁移断路失效的研究较多,但是对于析出效应(短路失效)的研究较少.研究发现在金属电迁移析出效应监测过程中易产生两种电介质击穿效应,分别为在实验刚开始发生的瞬时电介质击穿(TZDB)效应和测试过程中产生的时间依赖性电介质击穿(TDDB)效应.此外,电介质层材料的介电常数值越高,其耐电介质击穿的能力越高.析出效应的监测电场强度的设定值应该同时考虑电介质层材料与测试结构的特性,监测电场强度的设定范围建议为0.15～0.24 MV/cm,以防止在析出效应监测过程中发生电介质击穿,混淆两种不同的失效机理,造成误判.     

Electromigration-induced UBM consumption and the resulting failure mechanisms in flip-chip solder joints

Eutectic PbSn flip chip solder joint was subjected to 5×10³ A/cm² current stressing at 150°C and 3.5 × 10⁴ A/cm² current stressing at 30°C. The under bump metallurgy (UBM) on the chip was sputtered Ni/Cu, and the substrate side was a thick Cu trace. It was shown through in-situ observation that the local temperature near the entrance of electrons from the Al interconnect to the solder became higher than the rest of the joint. The accelerated local Ni UBM consumption near the entrance was also observed. Once the Ni was consumed at a location, a porous structure formed, and the flow of the electrons was blocked there. It was found that the formation of the void and the formation of the porous structure were competing with each other. If the porous structure formed first, then the void would not be able to nucleate there. On the other hand, if the void could nucleate before the UBM above lost its conductivity, then the joint would fail by the void formation-and-propagation mechanism.     

电迁移物理模型参数统计特性提取新方法

随着ＶＬＳＩ技术的发展，电迁移已成为集成电路最主要的失效原因之一，其可靠性评估技术也显得愈加重要。要改进该技术，不仅需要确定可靠性物理模型参数，而且要求掌握参数的统计分布特性。基于电迁移物理模型，提出一种提取参数统计分布特性的新方法。与传统方法相比，此方法不仅所需实验样品少、实验次数少，能真正得到反映样品离散性的物理模型参数的统计分布特性，而且也可用于其它失效机理（如栅氧击穿）物理模型中。     

Current-Induced Phase Partitioning in Eutectic Indium-Tin Pb-Free Solder Interconnect

Structural changes from high-density electric currents were examined in a eutectic In-Sn/Cu interconnect. Under electrical loading, Sn and In migrated in opposite directions, creating a partition of the Sn- and In-rich phases between the anode and the cathode. At the anode, a net gain of Sn atoms resulted in the formation of massive, columnar hillocks on the surface, but a net loss of In led to dissolution and disappearance of the In-rich intermetallic layer. At the cathode, the exodus of Sn left valleys adjacent to the In-rich regions on the surface, while the amount of the In-rich phase grew, due to the net influx of In at the expense of the In-rich intermetallic layer.     

Electromigration in aluminum/silicon/copper metallization due to the presence of a thin oxide layer

The effect of a thin layer of SiO₂ (50 nm) on the electromigration behavior of Al/ 0.8wt.%Si/0.5wt.%Cu metallization, passivated by spin-on-glass, phosphorus silicate glass and silicon nitride as part of the complementary metal oxide semiconductor technology fabrication process was studied. It is found that voids were formed along the edge of the metallization line as opposed to formation at triple point of grain boundaries. At the same stress current of 1 × 10⁶ A/cm², thicker metallization layer (600 nm) showed an improvement in median time to failure (MTF) (1.4 times) with smaller void size (0.2 to 0.4 μm) over one without an underlying oxide, whereas if the metallization thickness is thin (300 nm), the MTF is degraded (0.6 times) with larger void size formed (0.3 to 1.0 μm).     

Electromigration and mechanical stress in aluminium conductor tracks passivated by anodisation

The electromigration lifetime of integrated circuit metallisation is commonly found to increase if the metallisation is covered with a passivation layer such as glass. We have investigated the electromigration behaviour of aluminium conductor stripes under different thicknesses of oxide passivation formed by anodisation. The ionic drift velocity of anodised stripes was measured using the Blech-Kinsbron edge displacement technique (Thin Solid Films 25 327 (1975)) and it was found that the drift velocity decreased with increasing anodisation thickness. Stripes tested with a reversed current drifted backwards with an initial velocity which exceeded the original forward velocity. These results are related to a change in the self-diffusivity of aluminium as a result of high compressive stresses imposed by the anodised layer, and the distribution of stress in a drifting stripe is discussed. A general conclusion is that passivation layers can support compressive stresses sufficient to retard mechanical failure processes in metallisation in two distinct ways, either by raising the threshold stress for the nucleation of damage such as hillocks or whiskers, or by reducing the diffusivity in the metallisation.     

Lattice electromigration in narrow Al alloy thin-film conductors at low temperatures

At low temperatures, electromigration in polycrystalline Al thin-film conductors has been considered to occur predominantly along grain boundaries. As conductor widths decrease below the average grain size, however, other transport mechanisms will become important. Here we examine electromigration transport mechanisms in narrow AlSiCu conductors in the temperature range 190 to 290°C using the stripe drift technique. For conductors with widths between 0.9 and 2.75 μm both the absolute values of the drift velocity and the activation energy for drift are consistent with a lattice diffusion mechanism. Over this linewidth range the Al microstructure ranges from near-bamboo to approximately 20 μm long polycrystalline segments. The independence of the drift data from the linewidth shows that steady state transport is controlled by the bamboo regions of the conductors, which results from the slower rate of diffusion of Al through the lattice compared to along grain boundaries.     

热循环条件下Sn基钎料接头电迁移行为研究

通过电迁移和热疲劳循环实验,研究了热循环和高电流密度耦合作用下Sn58Bi和Sn3.0Ag0.5Cu钎料焊接接头的失效形式。实验结果表明,在通电和高低温冲击的耦合作用下,两种钎料接头的失效都发生在升温阶段。热循环导致接头内部裂纹的萌生和扩展,导致局部电流密度持续增大,加速了电迁移的发生,最终导致焊点失效。在热电耦合作用下,Sn58Bi钎料接头的使用寿命要长于Sn3.0Ag0.5Cu钎料接头的使用寿命。     

Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.