分立晶体管与TTL门电路的饱和输出状态的比较分析*

在高校的《数字电路》课程教学中，通常要对分立NPN晶体管和TTL门电路的低电平输出近饱和、饱和以及退饱和状态进行讲解，其中出现了貌似矛盾的现象。本文给出了两种情况下的比较分析，力图廓清对它们模棱两可的理解，并尝试给出了“被动饱和”与“主动饱和”两个新概念，建议了更为合理的饱和深度的定量表达式，以期对相关的教学以及教材编写起到积极的作用。     

选择性电极型晶硅太阳能电池金属栅线印刷位置精度的检测方法

本文提出一种金属栅线印刷位置的检测方法，适用于直接检测金属栅线印刷位置与选择性重扩散栅线印刷区的重合精度，可以实时在线检测栅线印刷位置精度并反馈偏差值，实现对位印刷的闭环控制。该检测方法同时也为采用图形识别技术和图形对位技术的选择性电极型晶硅太阳能电池丝网印刷设备提供了可直观衡量设备印刷精度的验证方法。此外，利用该检测方法可以实现对网板使用寿命的监测，提高网板和丝网印刷设备的使用率，降低生产成本，简化工艺控制。     

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high I_ON/I_OFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.     

PLBMAP:高性能通用FPGA可编程逻辑块映射算法

研究了一种低复杂度、高利用率、高性能的通用FPGA逻辑块映射算法,基本思想包括为降低算法复杂度而提出的将组合电路与时序电路分开映射、对逻辑单元分层;引入匹配度系数以提高逻辑单元的利用率,从而在算法的性能和速度两方面均得到了较好的突破:平均性能比现存通用映射算法提高了12.59%,平均运行时间可以降低102～103倍.     

Acoustic plasmons and composite hole-acoustic plasmon satellite bands in graphene on a metal gate

We demonstrate that single-layer graphene in the presence of a metal gate displays a gapless collective (plasmon) mode that has a linear dispersion at long wavelengths. We calculate exactly the acoustic-plasmon group velocity at the level of the random phase approximation and carry out microscopic calculations of the one-body spectral function of such systems. Despite screening exerted by the metal, we find that graphene’s quasiparticle spectrum displays a very rich structure characterized by composite hole-acoustic plasmon satellite bands (that we term for brevity “soundarons”), which can be observed by e.g. angle-resolved photoemission spectroscopy.     

The pushing gate in a planar Coulomb crystal using a flat-top laser beam

We propose a pushing gate for entangling two ions in a planar Coulomb crystal in the view of realizing large-scale quantum simulations. A tightly focused laser is irradiated from the direction perpendicular to the crystal plane and its spatial intensity profile generates a state-dependent force. We analyze the error sources in this scheme and obtain low infidelity.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a...