Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si量子信道 异质结构 CMOSFET 量子论 量子阱strained SiGe/Si, quantum well channel, heterostructure CMOSFET, poly-SiGe gateProject supported by the Preresearch from National Ministries and Commissions (Grant Nos 51408061104DZ01, 51439010904DZ0101).2/2/2006 12:00:00 AM2006-01-022006-03-16A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Sil-xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including： 1） the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2） the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3） better transistor matching; and 4） flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.     

The non—local implementation of a CNOT gate and single—qubit rotation

We show how a CNOT gate and single-qubit rotation can be implemented non-locally,We also report on the quantitative relations between these quantum actions,entanglement and classical communication resources required in the implementation.     

Normally Ordered Quantum Gate Operators for Continuum Variables as Images of Classical Transforms

We derive normally ordered quantum gate operators for continuum variables by mapping classical transforms onto Fock space. Successive gate operations can be treated in a unified way that is using the technique of integration within an ordered product of operators.     

Implementation of non-local multiple qubits controlled-not operation via partially entangled channels

We propose two different schemes for probabilistic implementing a non-local multiple qubits controlled-not operation via partially entangled quantum channels. The overall physical resources required for accomplishing these schemes are different, and the successful implementation probabilities are also different.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

散射介质成像中的时间门研究

研究了用蒙特卡罗方法模拟均匀散射介质中含有光学性质不同的小球时,漫反射信号随时间的变化,当小球和激励源的相对位置不同时随时间变化的漫反射曲线也不同,利用这种漫反射信号的差异同时结合时间门技术可以对散射介质中一定浓度的物体成像。结论表明成像对比度与时间门的开始时刻和时间门宽度有直接关系。针对小球投影位置漫反射信号的强和弱,分别用半宽度点和最大强度的80％点作为小球办界位置的判断。     

分立晶体管与TTL门电路的饱和输出状态的比较分析*

在高校的《数字电路》课程教学中，通常要对分立NPN晶体管和TTL门电路的低电平输出近饱和、饱和以及退饱和状态进行讲解，其中出现了貌似矛盾的现象。本文给出了两种情况下的比较分析，力图廓清对它们模棱两可的理解，并尝试给出了“被动饱和”与“主动饱和”两个新概念，建议了更为合理的饱和深度的定量表达式，以期对相关的教学以及教材编写起到积极的作用。     

选择性电极型晶硅太阳能电池金属栅线印刷位置精度的检测方法

本文提出一种金属栅线印刷位置的检测方法，适用于直接检测金属栅线印刷位置与选择性重扩散栅线印刷区的重合精度，可以实时在线检测栅线印刷位置精度并反馈偏差值，实现对位印刷的闭环控制。该检测方法同时也为采用图形识别技术和图形对位技术的选择性电极型晶硅太阳能电池丝网印刷设备提供了可直观衡量设备印刷精度的验证方法。此外，利用该检测方法可以实现对网板使用寿命的监测，提高网板和丝网印刷设备的使用率，降低生产成本，简化工艺控制。     

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high I_ON/I_OFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16 nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.     

PLBMAP:高性能通用FPGA可编程逻辑块映射算法

研究了一种低复杂度、高利用率、高性能的通用FPGA逻辑块映射算法,基本思想包括为降低算法复杂度而提出的将组合电路与时序电路分开映射、对逻辑单元分层;引入匹配度系数以提高逻辑单元的利用率,从而在算法的性能和速度两方面均得到了较好的突破:平均性能比现存通用映射算法提高了12.59%,平均运行时间可以降低102～103倍.