用FPGA实现智能复接器的小型化

介绍现场可编程门阵列（ＦＰＧＡ）的性能特点及其在工程应用中的设计过程，介绍△Ｍ制式数字程控交换机复接器的工作原理，最后给出一个在实陈工程中用ＦＰＧＡ实现智能复接器小型化的设计实例和设计结果。     

量子计算机前瞻:量子门与量子电路模型

本文介绍了量子计算机的基本概念和历史背景，它相对于经典计算机的优越性，详细讨论了量子逻辑门的基本构造，重点分析了单比特量子们和异或XOR门的控制受控关系，并对异或XOR门作为基本的2比特量子门的原因作了阐述，给出基于单比特量子门和XOR门构建的基它布尔逻辑门的量子电路。     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

超导逻辑门JAWS的电压态特性分析

本文是在数值分析基础上，用节点相位差的线性近似对ＪＡＷＳ门的非线性状态方程进行线性化，由此获得了门电压态特性的解析描述。其结果与数值分析非常一致，并揭示了门的隔离特性、扇出和电压态上叠加的高频振荡特性与门电路参数之间的关系。电压态振荡源于约瑟夫逊结的超流分量，因此它同样可存在于由约瑟夫逊结构成的以电压为状态特征的超导逻辑门中。     

凹槽拐角对深亚微米槽栅PMOSFET特性的影响

为优化槽栅器件结构 ,提高槽栅 MOSFET的性能和可靠性 ,文中用器件仿真软件对凹槽拐角对深亚微米槽栅 PMOSFET的特性影响进行了研究。研究结果表明凹槽拐角强烈影响器件的特性 :随着凹槽拐角的增大 ,阈值电压上升 ,电流驱动能力提高 ,而热载流子效应大大减弱 ,抗热载流子性能增强 ,热载流子可靠性获得提高 ;但凹槽拐角过大时 (例如 90°) ,器件特性变化有所不同     

Process optimization of polymetal (W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-µm technology

This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megabit, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-to-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finally, the temperature dependence of the data retention of the chips employing polymetal- and polycide-gates demonstrated the results to be quite comparable to each other.     

Test generation by activation and defect-drive (TEGAD)

This paper describes an efficient test generation method based on activation and defect-drive using random patterns. The activation process generates patterns to control any circuit node to 0 and 1. After the activation process, the defect-drive propagates the faulted signal, step by step, towards the external output by using parallel fault simulation. The applications are discussed for several gate arrays and micro-processors. The computer run time for the test generation was observed to be proportional to the number of nodes to the power of 1.7 in the case of bit-slice microprocessors. The improvement in manual patterns by the addition of the generated ones was also demonstrated.     

Optical Image Combination and Logic AND Operation Using Beam Fanning Effect

Using the beam fanning effect in a BaTiO₃ crystal, we propose two simple set-ups to perform the function of an optical image combiner and an optical AND gate respectively. The optical image combiner combines two mutually coherent as well as mutually incoherent patterns transmitted to it separately into a single coherent pattern. This set-up can also be used as an optical OR gate. For the AND gate, the two input signals may also be mutually coherent or incoherent. Experimental results showed the response time of these two devices to range from 0.01 second to 2.5 seconds.     

电子束直写直栅和T形栅工艺技术应用

介绍了用电子束直写技术在GaAs圆片上制作≤0.5μm栅和T形栅的工艺技术,并在GaAs器件的研制中得到应用。     

可综合算术运算单元的性能建模及VLSI结构优化

提出了一种可综合算术运算单元的性能评估与建模方法.该方法以单位门面积及延迟模型为基础,在设计的早期即可估算电路的面积、延迟等性能指标,从而便于设计者进行VLSI结构的优化,避免设计叠代;并以算术运算中最典型的二进制加法器为例,研究如何利用该模型对电路的VLSI实现结构进行评估、优化;理论分析的结论与电路的实现结果吻合,验证了该方法的有效性.