Fabrication of Superjunction Trench Gate Power MOSFETs Using BSG‐Doped Deep Trench of p‐Pillar

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n drift layer due to the trenched p‐pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.     

Fabrication of a planar water gated organic field effect transistor using a hydrophilic polythiophene for improved digital inverter performance

A planar water gated OFET (WG-OFET) structure is fabricated by patterning gate, source and drain electrodes on the same plane at the same time. Transistor output characteristics of this novel structure employing commercial regioregular poly(3-hexylthiophene) (rr-P3HT) as polymer semiconductor and deionized (DI) water as gate dielectric show successful field effect transistor operation with an on–off current ratio of 43 A/A and transconductance of 2.5 μA/V. These output characteristics are improved using P3HT functionalized with poly(ethylene glycol) (PEG) (P3HT-co-P3PEGT), which is more hydrophilic, leading to on–off ratio of 130 A/A and transconductance of 3.9 μA/V. Utilization of 100 mM NaCl solution instead of DI water significantly increases the on–off ratio to 141 A/A and transconductance to 7.17 μA/V for commercial P3HT and to 217 A/A and to 11.9 μA/V for P3HT-co-P3PEGT. Finally, transistors with improved transconductances are used to build digital inverters with improved characteristics. Gain of the inverters employing P3HT and P3HT-co-P3PEGT are measured as 2.9 V/V and 10.3 V/V, respectively, with 100 mM NaCl solution.     

一种双路图像融合实时处理系统的设计

提出了一种关于双路图像融合实时处理系统的设计,介绍了融合处理系统的总体架构和系统的功能。对系统的硬件设计和软件设计分别进行了说明,硬件设计对电源设计、采集模块设计和处理模块设计进行了详细阐述;软件部分细致分析了现场可编程门阵列(FPGA)的设计和数字信号处理器(DSP)的设计。最后对处理系统进行了测试,表明该设计满足实时处理的需求。同时,可对系统进行扩展,实现更多路图像的融合处理。     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

AlGaN/GaN HEMT场板结构对与表面态相关的延迟特性的影响

为了研究AlGaN/GaN HEMT器件中场板结构对电流崩塌效应影响的物理机理,我们运用数值模拟的方法研究了场板结构和与表面态相关的栅延迟现象之间的关系。模拟显示场板结构可以显著地抑制电流崩塌效应的强度,但是对延迟时间没有影响。场板结构可以增大AlGaN表面附近的空穴积累,导致表面态的离化率增大从而抑制器件的电流崩塌。     

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L₁) for a given gate length (L) are also studied and the optimum lengths L₁ under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.     

磁耦合元胞自动机逻辑器件的形状可重配置结构

磁耦合元胞自动机逻辑器件(即纳磁体逻辑器件)是后CMOS时代的一种极具潜力的新技术,具有无引线集成、极低功耗和天然非易失性等优点.纳磁体逻辑器件由纳米级单畴磁体构成,而磁体的形状是其一个重要的器件特征参数.本文研究了不同特殊形状纳磁体的转换特性,获得了改变特殊形状器件状态的时钟场值.提出了基于不同尺寸特殊形状纳磁体的可重配置择多逻辑门,采用OOMMF软件验证了形状择多逻辑门的输入可重配置性,得到了顺序配置不同输入组合所需的时钟场.该可重配置门结构的提出为磁性可编程逻辑计算电路的实现奠定了重要的理论基础.     

基于SOA-XGM效应的双逻辑门叠加结构研究

为了提高光传输系统数据信息的机密性与安全性,开展了光传输系统物理层全光加/解密技术的理论分析,设计了全光AB逻辑实验方案,通过结构相同的两全光AB逻辑门输出信号的耦合,实验实现了对速率为10Gb/s的明文光信号的全光加密。     

带电子聚焦的氧化锌场发射背光源

液晶显示需要低功耗、均匀度好的光源作为背光源。为了降低功耗,提高显示图像质量,未来的液晶显示需要实现对背光源进行时间与阵列调制。对比现有的液晶显示用背光源,研究制备了氧化锌场发射光源。该光源采用氧化锌纳米针作为场发射阴极,采用平面栅极作为门电极调制结构实现亮度的连续可调,通过带有氧化镁二次电子发射层的金属栅网对电子进行聚焦实现光源的均匀照度。实验结果表明,带电子聚焦的氧化锌场发射光源具有较低的开启场强(1.1V/μm),较小的电压调制区间(小于150V),较高的发光强度(大于1 000cd/m2),且基于电子聚焦结构的设计,实现了光源的均匀稳定照度,可以提高液晶显示的图像质量。带电子聚焦结构的氧化锌场发射光源,既可实现对发光的时间与阵列调制,同时能提高发光的均匀性,将可作为液晶显示的理想背光源。     

基于高非线性Sagnac干涉仪的超高速全光NOT门可级联性研究

在未来的通信领域中,全光逻辑门是全光计算机和全光网络的基本单元。目前已经提出了很多实现全光逻辑门的结构和方法,但是全光逻辑的技术瓶颈也出现了,就是怎样能够将单个的全光逻辑门级联起来实现更复杂的逻辑关系。现存的全光逻辑门结构一般不具有很好的可以实现多级连接的级联性,而且现有的对于级联性的分析大都停留在理论层面,而没有与实际情况相结合,所以对于实际应用来说意义很小。提出了一种新型的基于高非线性Sagnac 干涉仪的超高速全光NOT 门,建立了它的数学模型,采用了与实际情况更加接近的高斯脉冲模拟输入光,并且在仿真结果的基础上分析了系统的级联性,对级联性的分析考虑了光纤损耗和走离效应的影响。得到的基本结论表明,所提出的全光逻辑门的结构能够在实际情况下保持良好的级联性。