应变Si NMOSFET漏电流解析模型

基于应变Si/SiGe器件结构,本文建立了统一的应变Si NMOSFET漏电流解析模型. 该模型采用平滑函数,实现了应变Si NMOSFET漏电流及其导数,从亚阈值区到强反型区以及从线性区到饱和区的平滑性,解决了模型的连续性问题. 同时考虑了载流子速度饱和效应和沟道长度调制效应的影响,进一步提高了模型精度. 通过将模型的仿真结果和实验结果对比分析,验证了所建模型的有效性. 该模型可为应变Si数字集成电路和模拟集成电路分析、设计提供重要参考. 关键词： 应变Si NMOSFET 漏电流 解析模型     

非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET的解析模型

为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合.     

Performance enhancement of CMOS terahertz detector by drain current

In this paper, we study the effect of the drain current on terahertz detection for Si metal-oxide semiconductor fieldeffect transistors(MOSFETs) both theoretically and experimentally. The analytical model, which is based on the smallsignal equivalent circuit of MOSFETs, predicts the significant improvement of the voltage responsivity Rv with the bias current. The experiment on antennas integrated with MOSFETs agrees with the analytical model, but the Rv improvement is accompanied first by a decrease, then an increase of the low-noise equivalent power(NEP) with the applied current. We determine the tradeoff between the low-NEP and high-Rv for the current-biased detectors. As the best-case scenario, we obtained an improvement of about six times in Rv without the cost of a higher NEP. We conclude that the current supply scheme can provide high-quality signal amplification in practical CMOS terahertz detection.     

Stress analysis of Si1−xGex embedded source/drain junctions

The purpose of this paper is to evaluate the impact of the geometry of embedded Si_1−xGe_x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si_1−xGe_x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.     

短沟道MOSFET解析物理模型

本文基于修正的二维泊松方程导出了适用于深亚微米ＭＯＳＦＥＴ的值电压解析模型,并进而通过反型区电荷统一表达式并考虑到载流子速度饱和、ＤＩＢＬ、相关迁移率、反型层电容和沟道长度调制等主要小尺寸与高场效应,最后得以了较为准确、连续和可缩小的漏极电流模型,模型输出与华晶等榈测试ＭＩＮＩＭＯＳ模拟结果较为吻合,可用于ＶＬＳＩ器件与电路预测模拟。     

低导通电阻和栅漏电的高性能InAlN/GaN HEMT

本文制备了100nm栅长的InAlN/GaN HEMT。通过氧处理和优化欧姆接触获得了高性能的InAlN/GaN HEMT。所制备的器件在栅压偏置为2V时,漏端输出电流密度达到2.18A/mm。器件的导通电阻为1.49Ω*mm。与常规器件相比,器件的栅漏电下降了两个数量级。器件也获得良好的射频特性,电流截止频率和最高震荡频率分别为81GHz和138GHz。根据现有的报道,这是国内较早报道GaN基HEMT电流密度超过2A/mm。     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

High abstraction level CAD tool implementation of MOS drain current models

This paper presents a toolbox in which a compact high abstraction level formulation of the MOS drain current was implemented. The formulation is based on the popular ACM compact MOS model: the approximations introduced in the model preserve the drain-to-source device symmetry and the continuity between all regions of operation (i.e. weak, moderate and strong inversion). The technological parameters involved in the formulation are obtained by means of a fully automatic extraction procedure. Finally, a detailed case study, in which a behavioural analysis of sample-and-hold circuits using the proposed toolbox is performed, is presented. The ATMEL^® CMOS process was used as reference for the case study. The MATLAB^® environment was used to implement the drain current model formulation, the technological parameters extraction and the case study as well.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

基于漏区边界曲率分析的射频RESURF LDMOS耐压与导通电阻优化

分析了漏区边界曲率半径与射频RESURF LDMOS击穿电压的关系,指出漏区边界的弯曲对RESURF技术的效果具有强化作用.理论分析与模拟结果表明,满足RESURF条件时,提高漂移区掺杂浓度或掺杂深度的同时相应减小漏区边界的曲率半径,可以在维持击穿电压不变的前提下,明显降低导通电阻.