Optimization of electrohydrodynamic-printed organic electrodes for bottom-contact organic thin film transistors

In this study, we investigate the optimization of printed (3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) as source/drain electrodes for organic thin film transistors (OTFTs) through electrohydrodynamic (EHD) printing process. The EHD-printed PEDOT:PSS electrodes should fulfill the prerequisites of not only high conductivity but also optimum surface tension for successful jetting. The conductivity of PEDOT:PSS was dramatically enhanced from 0.07 to 352 S/cm by the addition of dimethylsulfoxide (DMSO). To use the DMSO-treated PEDOT:PSS solution in the EHD printing process, its surface tension was optimized by the addition of surfactant (Triton X-100), which was found to enable various jetting modes. In the stable cone-jet mode, the patterning of the modified PEDOT:PSS solution was realized on the surface-functionalized SiO₂ substrates; the printed line widths were in the range 384 to 81 μm with a line resistance of 8.3 × 10³ Ω/mm. In addition, pentacene-based OTFTs employing the EHD-printed PEDOT:PSS as source and drain electrodes were found to exhibit electrical performances superior to an equivalent vacuum-deposited Au-based device.     

Influence of a drain field plate on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor

In this paper,the influence of a drain field plate(FP)on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor(HEMT)is investigated.The HEMT with only a gate FP is optimized,and breakdown voltage VBRis saturated at 1085 V for gate–drain spacing LGD≥8μm.On the basis of the HEMT with a gate FP,a drain FP is added with LGD=10μm.For the length of the drain FP LDF≤2μm,VBRis almost kept at 1085 V,showing no degradation.When LDFexceeds 2μm,VBRdecreases obviously as LDFincreases.Moreover,the larger the LDF,the larger the decrease of VBR.It is concluded that the distance between the gate edge and the drain FP edge should be larger than a certain value to prevent the drain FP from affecting the forward blocking voltage and the value should be equal to the LGDat which VBR begins to saturate in the first structure.The electric field and potential distribution are simulated and analyzed to account for the decrease of VBR.     

PCB企业要在“降污减排”上“升级”和打漂亮仗

文章概述了PCB企业在生产和发展的过程中必须坚持“环保优先”原则,在“降污减排”和“清洁生产”上不断“升级”,坚决走PCB“清洁生产”的世界强国的道路!     

印制板行业大浪淘沙的时候到来了——解读“节能减排，优化升级”

文章叙述在当前强势环保,铁腕治污,严格执行环境影响评价的形势下,国家近来又推出“节能减排,一票否决”的新举措,印制板行业大浪淘沙的时候到来了。印制板行业必须积极响应,实施节能减摧,清洁生产,总量控制,达标排放,优化升级。     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

样品电流模式下外磁场引起的X射线吸收谱强度变化

在用样品电流模式的测量过程中发现，磁场强度、磁场与样品表面的夹角以及光斑在样品表面的位置都会对吸收谱强度产生影响；在光斑、磁场和样品的不同几何配置下,测量并分析了表面均匀氧化的铝箔中氧的K边吸收谱，指出外磁场下吸收谱强度随各种条件变化的趋势，并对实验结果给出了合理解释；结果表明所用的模型分析与实验数据符合得很好；所得到的信息对于XMCD实验的设计安排、相应数据的分析以及物理信息的提取具有重要意义.     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

毫米波三端器件漏极混频器的研究

对Ka频段三端器件漏极混频器电路进行了分析和优化设计。由三端器件小信号S参数和直流特性测试值拟合出该器件非线性等效电路模型和参数;采用谐波平衡和变换矩阵分析法推导出漏极混频器变频增益,由此优化设计混频器电路。实验测试结果射频为27.4GHz、本振为33.4GHz/10dBm,获得变频增益为4dB。     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.     

基于传统的CMOS工艺延伸漏极NMOS功率管研究

延伸漏极N型MOS（EDNMOS）是基于传统低成本CMOS工艺设计制造,用N-well作为NMOS漏极漂移区,以提高其击穿电压。用二维器件模拟软件Medicici对该器件进行模拟分析,结果表明有效地提高了NMOS管击穿电压。实验结果表明采用这种结构能使低压CMOS工艺输出功率管耐压提高到电源电压的2．5倍,样管在5V栅压下输出的电流可达到750mA。作为开关管工作,对于1000pF容性负载,其工作电流在550mA时,工作频率可达500KHz。