视频解码器中插值与加权预测的硬件实现

设计了支持H.264/JVT/AVC标准和AVS标准的插值与加权预测的硬件结构。整个设计在其所属的视频解码器中是以宏块为单位处理的,内部则以可变块为单位处理。为了提高插值的速度,双向预测并行处理,在插值模块的内部则做6级流水(H.264)或8级流水(AVS)。加权预测同样也做了4级流水。整个设计在Modelsim下的仿真结果正确,用XST在VIRTEXⅡ4000,-6上综合频率为98 MHz,所用SLICE约为10 000,预期整个解码器设计能支持1080i@30fps的高清实时解码。     

预测校正型曼Ⅱ码译码器技术研究与实现

文章针对计算机系统中串行总线的通讯,提出并实现了一种预测校正型曼Ⅱ码译码器.以预测校正型方式实现的曼Ⅱ码译码器,极大的提高了总线通讯的可靠性,节省了硬件资源,提高了系统的速度.该译码器已经应用于1553B总线控制器LS-FT33中,至今运行可靠.     

DVB-S信道内码解码器的FPGA实现

采用基于软件流水线的回溯法实现维特比译码中的幸存路径管理,从而有效节省了资源消耗,并提高了译码速度；从DVB-S解码器的整体系统结构考虑,使用一种高效的同步头锁定及内码信息确定的方案。整个设计在Xilinx公司的XC2VP30上实现。     

一种用模拟LSI实现的新型概率解码器的研究

本文利用工作在亚阈值模式的MOS管特性,设计了一种低功耗的模拟电流型乘法器,并以此乘法器为核心,设计了一组利用电流进行概率计算的模拟单元电路.根据这些单元电路,基于最大后验概率算法(MAP),实现了(5,2,3)格码软判决译码的概率解码器.在解码器的输入部分设计了新型的具有流水线结构的串行输入接口.用标准的0.6μm CMOS工艺对解码器进行了性能模拟验证.     

5.8GHz无线宽带接入技术在工业监控领域的应用

目前,基于最新城域网标准IEEE802.16a的无线宽带接入产品日趋成熟,高速无线以太网桥工作在5.8GHz频段,支持点对点和点对多点的网络结构,空中速率高达72Mbit/s,最远通信距离可达50km,完全能满足图像、语音、数据的传输要求。文章介绍了基于5.8GHz无线宽带接入方式设计的无线图像、语音、数据综合监控系统,对其原理和各部分结构进行了详细说明。     

用于数字音频广播接收机的全码率维特比译码集成电路

卷积编码维特比译码集成电路是数字音频广播接收机信道译码的关键部件．本文介绍了一种维特比译码集成电路的设计，该电路符合欧洲数字音频广播信道译码的标准要求，可对数字声音卷积编码的全部码率（8／9，…，1／2，…，1／3，…，1／4）进行译码，最高译码输出码率大于2048kbps，集成电路采用瑞典爱立信公司的P540．6μmCMOS工艺设计和制造，核心面积为10mm2，芯片总面积为25mm2，等效逻辑门数为27，000门测试结果表明芯片满足所有设计要求．目前已用于我们开发的数字音频广播接收机中．     

新颖的CMOS四值译码器与编码器

利用多级离子注入技术,一种新型的 C M O S 四值译码器与编码器被设计.它们有一 个低功耗与低输出阻抗的简单结构,可以用作超大规模集成电路设计中的接口电路,以减 少基片的外部引线数     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).     

Improved Performance of Maximum Likelihood Decoding Algorithm with Efficient Use of Algebraic Decoder

A new soft decision maximum-likelihood decoding algorithm, which generates the minimum set of candidate codewords by efficiently applying the algebraic decoder is proposed. As a result, the decoding complexity is reduced without degradation of performance. The new algorithm is tested and verified by simulation results.Panagiotis G. Babalis was born in Athens, Greece, on January 3, 1974. He received his Diploma of electrical and computer engineering and the Ph.D. degree, both from National Technical University of Athens (NTUA), Athens, Greece, in 1996 and 2001, respectively. His main research interests include mobile satellite communications, modulation, and wireless communications systems coding. Dr. Babalis is a member of the technical Chamber of Greece.Panagiotis T. Trakadas was born in Athens, Greece, on January 14, 1972. He received his Diploma of Electrical and Computer Engineering and the Ph.D. degree from National Technical University of Athens (NTUA), Athens, Greece, in 1996, and 2001, respectively. From 1998 to 2001, he participated in many European projects as a researcher. His main research interests include mobile communications systems and electromagnetic compatibility topics. Dr. Trakadas is a member of the Technical Chamber of Greece and IEEE Society.Theodore B. Zahariadis received his Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, and his Dipl.-Ing. Degree in computer engineering and information science from the University of Patras, Greece. Currently, he is the technical director of Ellemedia Technologies, where he leads R&D of end-to-end interactive multimedia services, embedded systems, and 3G/4G core network services. Since 1994 he has participated in many European co-funded projects. His research interests are in the fields of broadband wireline/wireless/mobile communications, interactive service deployment, management of IP/WDM networks, and embedded systems. He has published more than 30 papers. He has been a reviewer and principal guest editor in many journals and magazines. He is a member of the ACM and the Technical Chamber of Greece.Christos N. Capsalis was born in Greece, in 1956. He received the diploma in electrical and mechanical engineering from the National Technical University of Athens (NTUA), Athens, Greece, in 1979, the B.Sc. degree in economics from the University of Athens, Athens, Greece, in 1983, and the Ph.D. degree in electrical engineering from NTUA in 1985. He is currently a Professor at NTUA and Director of the wireless communications laboratory. His current research activities include wireless and satellite communications systems and EMC topics.     

基于AVS标准的熵解码器硬件设计

提出了一种基于AVS标准熵解码器的设计方案.采用桶形移位器进行移位,采用并行结构确定码长.采用算术方法对19张码表进行算术优化,从而减小了芯片面积,提高了解码速度.采用Verilog HDL语言进行源代码设计和仿真.在0.25 μmCMOS工艺库下,用Design Compiler进行综合,面积为1.5万门左右,最高频率达100 MHz,达到实时解码高清AVS码流要求.