新型多制式彩色解码IC—TA8659AN

本文介绍用于大屏幕，高画质彩电中的新型多制式彩色解码ＩＣ－ＴＡ８６５９ＡＮ各项分电路工作原理及引脚功能，着重介绍了新型图像清晰度提升电路，色副载波ＡＰＣ搜索电路及自动制式识别，优良的同步分离电路等技术。     

全数字PAL解码器的原理与应用

分析了全数字ＡＰＬ解码器的一般原理，并结合具体应用讨论了解码器与后面的数字处理部分之间的缓冲控制。     

基于施工电梯的N∶1无线呼叫系统

针对建筑施工电梯的工作需要，采用先进的编／译码器，研制成一种结构新颖、操作方便、成本低廉的Ｎ∶１无线呼叫通讯系统。文章介绍了系统的功能要求及各组成部分的设计原理。接收系统使用４片ＭＣ１４５０２７，可译出６４个楼层的呼梯信号。由于设计了一种独特的发射互锁环，有效地解决了多个楼层同时呼梯的冲突问题。本系统可用于建筑施工及其它场合。     

基于IEEE 802.11无线网络的媒体点播终端的研究与实现

提出了基于嵌入式处理器和IEEE802．11无线网络的一种媒体点播终端的设计方案，介绍了基于InterPXA270处理器的媒体终端的软硬件设计，并详细介绍了基于IPP库的MPEG-4解码器的设计。     

Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications

Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.     

A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process

The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency.     

用于局域网的OCDMA技术

文章基于光码分复用编／解码技术，阐述了光纤延迟线时域编／解码器和利用光栅的频域编／解码器；提出了一种两层网络的拓扑结构：在OCDMA星形局域网拓扑结构的基础上构造WDM环网。     

CMMB系统中高性能RS译码器的FPGA实现

采用便于实现并性能较好的BM算法,结合流水线技术,设计并实现了符合CMMB标准的时域译码器.实验证明,该译码器具有多码率复用、控制简单灵活、面积小、资源耗用少、工作速率高、数据吞吐量大等优点.     

CM8870DTMF解码器及其与8098单片机的接口设计

介绍了索利特朗公司（SOLITRON）生产的CM8870DTMF解码器的工作原理，给出了其与8098单片机的硬件接口电路及软件程序。     

具有ADC和DAC的MP3解码器

介绍了MP3解码器的特性、工作原理和应用电路。针对MP3解码器高精度和低功耗的技术要求，在片内使用一个新型32位浮点DSP核和高效率电源管理技术。