基于FPGA的高速Fast-SSC译码器测试系统

为了满足Polar码高性能测试时大数据量的要求,设计了一种针对Fast-SSC译码器的FPGA硬件测试平台,包含信源、信道编码器、调制器、信道、解调器、译码器和统计模块,采用Verilog在Altera Stratix V 5SGXEA7N2F45C2上实现,并采用PCIe接口与上位机进行通信。该平台对码长1024、码率1/2的Polar码进行测试,结果表明测试频率为300MHz、测试数据为1.4*1010 位时,译码耗时仅为19.18s。     

A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process

The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency.     

Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications

Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.     

LDPC码译码器的设计与实现

由于传统的LLR BP译码算法不易于FPGA实现,为了降低实现复杂度,采用一种改进的LLR BP译码实现方法,设计了一种码长为40、码率为0.5的规则LDPC码译码器,并完成了FPGA仿真实现.仿真和综合的结果表明,所设计的译码器吞吐量达到15.68 Mbit/s,且译码器的资源消耗适中.     

QR条码图像识别及解码技术的实现

在Windows平台下,研究了QR条码的识别方法及解码技术.在识别过程中,利用Hough变换进行边缘检测,计算QR图像的角度旋转并纠正图像失真,然后进行细化边缘处理,有效地抑制QR图像中的失真及噪声.在此基础上,设计开发出一套QR码解码软件.测试结果表明,该系统具备较高的解码性能,识别率高、速度快,而且CPU占用率较低.     

正交相位解码器

使用一个简单的状态机调整两个光电池的输出，以控制一个增／减计数器，状态机为计算部件正确提供了滞后作用，而不管方向的变化。     

OCDMA通信系统编/解码器技术

介绍了光延迟线编／解码器，给出了两种光延迟线变址方案并分析了它们的性能。提出了三种新的编／解码器设计方案：基于步进啁啾FBG(光纤布喇格光栅)的光谱编码器、二维光延迟线编／解码器和多FBG编/解码器。     

一种高速HUFFMAN解码电路

研究了HUFFMAN解码器在集成电路上的实现问题，以MPEG-2AAC(先进音频编码)HUFFMA为研究对象．在研究解码码表的特点以及简化解码算法的基础上设计出高速HUFFMAN解码电路。此解码电路已经在ALTERA的FPGA上通过测试。系统能稳定运行在100MHz，输出数据平均达到约1．0Gbits／sec的带宽。     

改进Turbo码译码器硬件实现的方法

简要描述了基于Log-MAP译码算法的MAP译码器结构,介绍了几种改善其硬件实现结构的途径:选择合理的计算顺序和进行适当简化方法;引入了滑动窗方法;给出了通过改变数据存储结构来减小存储器的大小的方法。分析了改进方法对译码性能和实现的影响。     

基于TMS320C6000的MPEG-4视频实时解码优化设计

介绍在TMS320C6000系列DSP上实现MPEG-4视频实时解码的优化方法。先对OpenDivxDecore做数据结构优化,有效减少了Decore对存储空间的要求。在此基础上,针对DSP的特点,在内外存储器分配、DMA数据搬移、软件流程等方面做专门优化。优化后的代码在TIC6711图像开发板(IDK)上运行的实验结果表明,在码率为800Kbps视频格式为CIF352×288的条件下,MPEG-4解码速度可达30～45fps。