A Novel Routing Protocol for Supporting QoS for Ad Hoc Mobile Wireless Networks

The main purposes of this article are to lessen the influence of the fastchanging network topology, rapidly varying bandwidth information, and the increasing size of routing tables onquality of service routing. Based on DSDV (Destination-Sequenced Distance-Vector) routing protocol formaintaining up-to-date routing information, the related research has to update routing tables when networktopology changes; moreover, the routing tables must be updated periodically even though the networktopology has not changed. To put emphasis on QoS routing, they also have to exchange routing tables by thetime of bandwidth information changes. Furthermore, the size of routing tables increases with the numberof mobile nodes; therefore, the precious wireless bandwidth is wasted on transmitting the large-scalerouting tables. In this article, we propose an on-demand-based QoS routing protocol to mitigate theseproblems and to achieve the QoS requirement. The goal of this article is to discover an optimal routewith minimum time delay for transmitting real-time data from a source node hop by hop to adestination node under some predefined constraints. Our contributions are as follows: our researchprovides a rigorous bandwidth definition and bandwidth application, a broad view of bandwidth calculationand reservation, minimizing the size of control packets and the number of control packet transmissions,and an efficient QoS routing protocol.     

5类电缆的制造及质量控制

本文主要介绍了永鼎集团利用现有设备生产高性能无屏蔽对绞电缆（ＵＴＰ）的实践,并从工艺的角度出发讨论５类缆的结构尺寸、电气性能及其制造。     

支持事务的非结构化数据聚合存储系统GSL

文章提出了一种将非结构化数据集中存储,同时支持事务的存储方案,并依据此方案实现了一个高效、易用的数据存储系统GSL。GSL的数据存储接口与文件系统的接口风格一致,同时支持事务处理。文章将GSL与文件系统和Oracle数据库的BLOB存储效率进行了测试和比较,结果表明GSL的存储效率与文件系统相当,并优于BLOB。     

数据加密技术在计算机安全中的应用分析

计算机网络应用广泛,不仅提高了人们的学习效率与工作效率,还可以提高人们查阅信息的速度,为人们提供便捷,同时,也实现了网络信息的公开化.因此,网络安全成为一个重要的问题,在实际运用中,了解计算机病毒以及网络黑客对网络的威胁性,分析计算机安全中存在的安全隐患,根据算法的结构、步骤,了解计算机加密技术在计算机安全中的应用,发挥数据加密技术在计算机安全中的作用具有重要价值.     

一种选择多小波预滤波器的方法

提出了多小波(Multiwavelet)预滤波器的选择原则—预滤波和多小波变换对原数据不引入任何形式的信息损失或失真,该原则对应于预滤波器和多小波滤波器组在频域内能谱密度恒为常数．在此基础上,得到了常用多小波预滤波器应满足的必要条件．提出了用于数据压缩的预滤波器的选择方法,该方法以数据高低频成分分离的分离效率为选择准则．以此准则,给出了常用多小波的最佳预滤波器．仿真实例证实了这种方法的有效性．     

一种新的克服OFDM技术中峰平比的方案

在OFDM技术中,PAPR(峰平比)过大的问题一直是人们研究的热点;作者利用一种新的CI/OFDM结构,通过选择合适的频率偏移,达到降低OFDM信号的峰平比的目的.通过对比分析了这种结构的可行性和有效性,并对其进行系统仿真.     

单片机系统中数据存储的可靠性研究

详细介绍了影响单片机系统数据存储可靠性的原因,从硬件和软件两个方面阐述了提高单片机系统数据存储可能性的具体方法。     

An improved reversible data hiding-based approach for intra-frame error concealment in H.264/AVC

As H.264/AVC video streams are highly compressed, they become sensitive to errors caused by unreliable transmission channels. In order to address this issue, an improved version of Chung et al.’s reversible data hiding-based approach for intra-frame error concealment is proposed for H.264/AVC codec. By using the histogram shifting technique, the original work reversibly embeds the motion vector (MV) of a macroblock (MB) into other MB within the same intra-frame. If an MB is corrupted at the decoder side, the embedded MV can be extracted from the corresponding MB for the recovery of the corrupted MB. However, Chung et al.’s work did not fully exploit the number of coefficients which need to be modified in order to reversibly hiding data, and did not consider many extra nonzero residual blocks produced by data hiding. These two issues could reduce the visual quality of the stego-video. This paper adopts MV data pre-processing, the selection of most suitable embedding region, and the minimum possible amount of histogram modification, which lead to higher PSNR of the stego-video for a given payload. Experimental results further reveal that the proposed method offers stego-video with better visual quality over Chung et al.’s work.     

Dynamically scalable dual-core pipelined processor

This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs. This design aimed to be implemented on Xilinx Spartan 3E XC3S500E FPGA.