Openly disjoint circuits through a vertex in regular digraphs

In 1985, Thomassen [14] constructed for every positive integer r, finite digraphs D of minimum degree δ(D)=r which do not contain a vertex x lying on three openly disjoint circuits, i.e. circuits which have pairwise exactly x in common. In 2005, Seymour [11] posed the question, whether an r-regular digraph contains a vertex x such that there are r openly disjoint circuits through x. This is true for r≤3, but does not hold for r≥8. But perhaps, in contrast to the minimum degree, a high regularity degree suffices for the existence of a vertex lying on r openly disjoint circuits also for r≥4. After a survey of these problems, we will show that every r-regular digraph with r≥7 has a vertex which lies on 4 openly disjoint circuits.     

Coupling induced logical stochastic resonance

In this work we will demonstrate the following result: when we have two coupled bistable sub-systems, each driven separately by an external logic input signal, the coupled system yields outputs that can be mapped to specific logic gate operations in a robust manner, in an optimal window of noise. So, though the individual systems receive only one logic input each, due to the interplay of coupling, nonlinearity and noise, they cooperatively respond to give a logic output that is a function of both inputs. Thus the emergent collective response of the system, due to the inherent coupling, in the presence of a noise floor, maps consistently to that of logic outputs of the two inputs, a phenomenon we term coupling induced Logical Stochastic Resonance. Lastly, we demonstrate our idea in proof of principle circuit experiments.     

利用超导量子电路模拟拓扑量子材料

近年来,探索新的拓扑量子材料、研究拓扑材料的新奇物理性质成为凝聚态物理领域的一个热点.但是,由于合成、测量等手段的限制,人们难以在真实材料中实现和观测很多理论预言的材料及其物理性质,促使量子模拟日益成为研究量子多体系统的一个重要手段.作为全固态器件,超导量子电路是一个在扩展性、集成性、调控性上都具有巨大优势的人工量子系统,是实现量子模拟的重要方案.本文总结了利用超导量子电路对时间-空间反演对称性保护的拓扑半金属、Hopf-link半金属和Maxwell半金属等拓扑材料的量子模拟,显示出超导量子电路在模拟凝聚态物理系统方面具有广阔前景.     

开关电源的缓冲电路设计

随着开关电源工作频率的提高,开关器件承受很大的热量和电应力,从而形成过电压。为此,常常需要设置各种缓冲电路对其进行抑制。重点分析比较了三种缓冲电路,并指出了各自的特点及设计要点。RCD缓冲电路的箝位电压随电阻减小而减小,但损耗增大;LCD缓冲电路的LC谐振频率要求小于开关频率;能量回馈缓冲电路的箝位电压较低,不需要额外的电感。最后,给出了LCD缓冲电路的设计结果,实现了无损耗箝位。     

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.     

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Summary  Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 μm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 μm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 μm HVCMOS technology to 0.18 μm and beyond as well as to currents of up to 8 A.      

GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路

利用GaAs基 E/D PHEMT 技术单片集成微波开关及其逻辑控制电路的制作工艺和设计方法,采用0.8μm GaAs E/D PHEMT工艺,制备出性能良好的解码器功能内置的DC~10GHz SPDT MMIC,基本实现逻辑电路与开关电路的集成. 开关电路在DC~10GHz内插入损耗小于1.6dB,隔离度大于24dB;整个电路只需要1位控制信号,有效地减少了开关电路的控制端口数目,节省了芯片面积,为GaAs多功能电路的研究奠定了基础.     

新型高速低功耗显式脉冲触发器电路设计

提出了两种新型脉冲触发器结构--EXPAND触发器和EXPAND-TG触发器. 同传统结构相比,新结构一方面通过减小中间节点电容提高电路充放电速度,另一方面通过消除信号竞争避免直流短路电流对电路速度和功耗的影响. 同其他文献报道的结构相比,新结构在功耗和速度上均有明显的改进.     

借助EWB仿真软件分析混沌电路

通过虚拟电子实验室EWB软件仿真了非线性系统产生的混沌现象,以Colpitts振荡器电路为例,讨论了在电路中设置不同的元件参数值时产生的不同混沌,并介绍了这种动态混沌在通信系统中作为信息载体的重要应用.     

Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits

This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.